clarify

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index 43b49ff846bd35dc3e420ae95450d066915e4fbc..1b99f95cdcc3d9a907a2636625eb50f20ffe06a4 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -681,7 +681,7 @@ loop:
             (scalar ops are just vectors of length 1)\vspace{4pt}
    \item Tightly coupled with the core (instruction issue)\\
          could be disabled through MISA switch\vspace{4pt}
-   \item An extra pipeline phase is pretty much essential\\
+   \item An extra pipeline phase almost certainly essential\\
          for fast low-latency implementations\vspace{4pt}
    \item With zeroing off, skipping non-predicated elements is hard:\\
          it is however an optimisation (and could be skipped).\vspace{4pt}