Fix SB_DFF comb model

diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v
index 1d104c5d78cd11d2aab6e28b62da2c8b195fb849..c49b29ab3f31e19d4a8c738d82de37e15b173ea8 100644 (file)
--- a/techlibs/ice40/cells_sim.v
+++ b/techlibs/ice40/cells_sim.v
@@ -143,7 +143,7 @@ module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) in
        always @(posedge C)
                Q <= D;
 `else
-    assign Q = D;
+    always @* Q = D;
 `endif
 endmodule
 

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 84abf71819558ea7062e1ba0719f501a482c529a..d5d3547013244c0303d8861d9f71065651b6e42e 100644 (file)
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass
        {
                if (check_label("begin"))
                {
-                       run("read_verilog -wb +/ice40/cells_sim.v");
+                       run("read_verilog -wb -D ABC_FLOPS +/ice40/cells_sim.v");
                        run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
                        run("proc");
                }
@@ -293,7 +293,7 @@ struct SynthIce40Pass : public ScriptPass
                                run("techmap");
                        else
                                run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
-                       if (retime || help_mode)
+                       if ((retime || help_mode) && abc != "abc9")
                                run(abc + " -dff", "(only if -retime)");
                        run("ice40_opt");
                }