update to comply with python-data layout

diff --git a/litex/soc/cores/cpu/blackparrot/README.md b/litex/soc/cores/cpu/blackparrot/README.md
index d320d4b4579b832244add8c2f54a52af1a579de9..95b10a1c3d1d3b908c6d3863d3310d270b497030 100644 (file)
--- a/litex/soc/cores/cpu/blackparrot/README.md
+++ b/litex/soc/cores/cpu/blackparrot/README.md
@@ -1,12 +1,22 @@
 TODO: Edit
-git submodule update --init --recursive (for blackparrot pre-alpha repo)
-cd pre_alpha_release
-follow getting_started to install blackparrot
-cd ..
 source ./setEnvironment.sh #should be sourced each time you open a terminal or just add this line to bashrc
 Add $BP_TOP/external/bin to $PATH for verilator and riscv-gnu tools
-./update_BP.sh #to modify some of the files in Blackparrot repo (one-time process)
 Currently, we could simulate the LITEX-BIOS on BP processor. 
 
+
+#TODO Running BIOS
+
+
+
+#TODO Running Linux
+
+
+
+#TODO Running on FPGA
+
+
+#TODO
+RISCV tool chain explanation (we currently support IA extension)
+
 [![asciicast](https://asciinema.org/a/286568.svg)](https://asciinema.org/a/286568)
 

diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index e1661bc07af6489dcd4c8a9606f14ad3a152c94e..5a9738d05d73013cb108bb34e0f95cffb3c0cf7e 100644 (file)
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -118,13 +118,13 @@ class BlackParrotRV64(CPU):
 
     @staticmethod
     def add_sources(platform, variant="standard"):
+        vdir = get_data_mod("cpu", "blackparrot").data_location
+        bp_litex_dir = os.path.join(vdir,"bp_litex")
         simulation = 0
         if (simulation == 1):
-            filename = get_data_mod("cpu", "blackparrot").data_file(
-            "flist.verilator")
+            filename= os.path.join(bp_litex_dir,"flist.verilator")
         else:
-            filename = get_data_mod("cpu", "blackparrot").data_file(
-            "flist.fpga")
+            filename= os.path.join(bp_litex_dir,"flist.fpga")
         with open(filename) as openfileobject:
             for line in openfileobject:
                 temp = line

diff --git a/litex/soc/cores/cpu/blackparrot/setEnvironment.sh b/litex/soc/cores/cpu/blackparrot/setEnvironment.sh
index 079bb17f79b28e6f42d631a7d09f87333838f09c..1e45ca903bd5e97aa48f39f7a6862b1a6e41a8c6 100755 (executable)
--- a/litex/soc/cores/cpu/blackparrot/setEnvironment.sh
+++ b/litex/soc/cores/cpu/blackparrot/setEnvironment.sh
@@ -1,98 +1,24 @@
 #!/bin/bash
 ## Set common environment variables
 export LITEX=$(git rev-parse --show-toplevel)
-export BP=$PWD
-cp bp_software/cce_ucode.mem /tmp/.
-cd pre-alpha-release
-TOP=$(git rev-parse --show-toplevel)
-export BP_COMMON_DIR=$TOP/bp_common
-export BP_FE_DIR=$TOP/bp_fe
-export BP_BE_DIR=$TOP/bp_be
-export BP_ME_DIR=$TOP/bp_me
-export BP_TOP_DIR=$TOP/bp_top
-export BP_EXTERNAL_DIR=$TOP/external
+export BP=$LITEX/../pythondata-cpu-blackparrot/pythondata_cpu_blackparrot/system_verilog
+export BP_LITEX_DIR=$BP/bp_litex
+export LITEX_SOFTWARE_COMPILER_RT=$LITEX/../pythondata-software-compiler_rt
+
+#TODO: check if BP exists and warn user
+export BP_COMMON_DIR=$BP/bp_common
+export BP_FE_DIR=$BP/bp_fe
+export BP_BE_DIR=$BP/bp_be
+export BP_ME_DIR=$BP/bp_me
+export BP_TOP_DIR=$BP/bp_top
+export BP_EXTERNAL_DIR=$BP/external
 export BASEJUMP_STL_DIR=$BP_EXTERNAL_DIR/basejump_stl
-export BP_FPGA_DIR=$TOP/bp_fpga
-## Setup CAD tools
+export LITEX_FPGA_DIR=$BP_LITEX_DIR/fpga
+export LITEX_SIMU_DIR=$BP_LITEX_DIR/simulation
+export LITEX_SOFTWARE=$BP_LITEX_DIR/software
 
-# If the machine you are working on is bsg_cadenv compliant, then you do not
-# need to setup the cad tools, simply put bsg_cadenv in the same root dir.
-#BSG_CADENV_DIR=$(TOP)/external/bsg_cadenv
-#-include $(BSG_CADENV_DIR)/cadenv.mk
+##SOFTWARE CHANGES##
 
-## Sepcify license path if needed
-#LM_LICENSE_FILE ?=
+#for a reason, provided udivmoddi4.c is not functionally correct when used with either BP or Rocket under IA extension. Another version of udivmoddi4.c is a workaround to run BIOS on these architectures.
+cp $LITEX_SOFTWARE/udivmoddi4.c $LITEX_SOFTWARE_COMPILER_RT/pythondata_software_compiler_rt/data/lib/builtins/.
 
-## Override tool paths if needed
-#GCC       ?= gcc
-#VCS_HOME  ?=
-#VCS       ?= vcs
-#URG       ?= urg
-#VERILATOR ?= verilator
-#DC_SHELL  ?= dc_shell
-#DVE       ?= dve
-#PYTHON    ?= python
-
-## Needed for verilator g++ compilations
-export SYSTEMC_INCLUDE=$BP_EXTERNAL_DIR/include
-export SYSTEMC_LIBDIR=$BP_EXTERNAL_DIR/lib-linux64
-
-## Add external tools and libraries to environment
-export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR
-#:$LD_LIBRARY_PATH
-#export PATH=$(BP_EXTERNAL_DIR)/bin:$(PATH)
-#export SYN_PATH=$(BP_TOP_DIR)/syn
-#export TB_PATH=$(BP_TOP_DIR)/test/tb
-#export MEM_PATH=$(BP_COMMON_DIR)/test/mem
-
-#export LOG_PATH=$(BP_TOP_DIR)/syn/logs
-#export RESULTS_PATH=$(BP_TOP_DIR)/syn/results
-#export REPORT_PATH=$(BP_TOP_DIR)/syn/reports
-
-TB="bp_top_trace_demo"
-CFG="e_bp_single_core_cfg"
-START_PC=0x80000000
-TOLERANCE=2
-
-# Select CCE ROM based on CFG and Coherence Protocol
-# TODO: is there a more scalable way to do this?
-if [ $CFG = "e_bp_half_core_cfg" ]
-then
-    NUM_LCE_P=1
-    N_WG=64
-elif [ $CFG = "e_bp_single_core_cfg" ]
-then
-    NUM_LCE_P=2
-    N_WG=64
-    #echo "Single Core config"
-#elif ($CFG -eq e_bp_dual_core_cfg)
-#    NUM_LCE_P=4
-#    N_WG=32
-#elif ($CFG -eq e_bp_quad_core_cfg)
-#    NUM_LCE_P=8
-#    N_WG=16
-#elif ($CFG -eq e_bp_oct_core_cfg)
-#     NUM_LCE_P=16
-#     N_WG=8
-#elif ($(CFG), e_bp_sexta_core_cfg)
-#    NUM_LCE_P=32
-#    N_WG=4
-#elif ($(CFG), e_bp_quad_core_2d_cfg)
-#    NUM_LCE_P=8
-#    N_WG=16
-#elif ($(CFG), e_bp_oct_core_2d_cfg)
-#    NUM_LCE_P=16
-#    N_WG=8
-fi
-
-COH_PROTO="mesi"
-CCE_MEM_PATH=$BP_ME_DIR/src/asm/roms/$COH_PROTO
-CCE_MEM=bp_cce_inst_rom_$COH_PROTO_lce$NUM_LCE_P_wg$N_WG_assoc8.mem
-#DRAMSIM_CH_CFG=DDR2_micron_16M_8b_x8_sg3E.ini
-#DRAMSIM_SYS_CFG=system.ini
-#$include $BP_COMMON_DIR/syn/Makefile.verilator
-#iinclude $(BP_COMMON_DIR)/syn/Makefile.common
-#include $(BP_COMMON_DIR)/syn/Makefile.dc
-#include $(BP_COMMON_DIR)/syn/Makefile.regress
-#include $(BP_COMMON_DIR)/syn/Makefile.vcs
-cd ../

diff --git a/litex/soc/software/bios/Makefile b/litex/soc/software/bios/Makefile
index 98dc44d52dac763128742761d53e09d053899d07..cc58ddf3a090b3cf4ad700c63abe4cb1a13b4d09 100755 (executable)
--- a/litex/soc/software/bios/Makefile
+++ b/litex/soc/software/bios/Makefile
@@ -2,7 +2,7 @@ include ../include/generated/variables.mak
 include $(SOC_DIRECTORY)/software/common.mak
 
 ifeq ($(CPU),blackparrot)
-BP_LIBS =  -L$(BP_EXTERNAL_DIR)/lib/gcc/riscv64-unknown-elf/9.2.0/ 
+BP_LIBS =  -L$(LITEX_SOFTWARE)
 BP_FLAGS = -lgcc
 endif
 # Permit TFTP_SERVER_PORT override from shell environment / command line

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 83c50793d077d2c8c652c4baffc48cc5fbdf56c9..86c6d9692d1a0edd80b40fd93b7fbd7b420330e5 100755 (executable)
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -353,7 +353,7 @@ def main():
         with_analyzer  = args.with_analyzer,
         sdram_init     = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu_endianness),
         **soc_kwargs)
-    if args.sdram_init is not None: #sdram_init
+    if args.ram_init is not None: #sdram_init
         soc.add_constant("ROM_BOOT_ADDRESS", 0x80000000)
     if args.with_ethernet:
         for i in range(4):