vendor.xilinx_{7series,spartan6}: cleanup. NFC.

Eliminate some intermediate signals if they are not necessary.
Do not even return i, o, or t if the pin does not have them.

diff --git a/nmigen/vendor/lattice_ice40.py b/nmigen/vendor/lattice_ice40.py
index da68c079e2ff39bafab6b3e920f8d116f33de710..be1e996af1e24d6c12b934fd25af438ca2fa937b 100644 (file)
--- a/nmigen/vendor/lattice_ice40.py
+++ b/nmigen/vendor/lattice_ice40.py
@@ -129,7 +129,7 @@ class LatticeICE40Platform(TemplatedPlatform):
                 i_D=d,
                 o_Q=q)
 
-        def get_i_inverter(y, invert):
+        def get_ixor(y, invert):
             if invert is None:
                 return y
             else:
@@ -144,7 +144,7 @@ class LatticeICE40Platform(TemplatedPlatform):
                         o_O=y[bit])
                 return a
 
-        def get_o_inverter(a, invert):
+        def get_oxor(a, invert):
             if invert is None:
                 return a
             else:
@@ -168,16 +168,16 @@ class LatticeICE40Platform(TemplatedPlatform):
 
         if "i" in pin.dir:
             if pin.xdr < 2:
-                pin_i  = get_i_inverter(pin.i,  i_invert)
+                pin_i  = get_ixor(pin.i,  i_invert)
             elif pin.xdr == 2:
-                pin_i0 = get_i_inverter(pin.i0, i_invert)
-                pin_i1 = get_i_inverter(pin.i1, i_invert)
+                pin_i0 = get_ixor(pin.i0, i_invert)
+                pin_i1 = get_ixor(pin.i1, i_invert)
         if "o" in pin.dir:
             if pin.xdr < 2:
-                pin_o  = get_o_inverter(pin.o,  o_invert)
+                pin_o  = get_oxor(pin.o,  o_invert)
             elif pin.xdr == 2:
-                pin_o0 = get_o_inverter(pin.o0, o_invert)
-                pin_o1 = get_o_inverter(pin.o1, o_invert)
+                pin_o0 = get_oxor(pin.o0, o_invert)
+                pin_o1 = get_oxor(pin.o1, o_invert)
 
         if "i" in pin.dir and pin.xdr == 2:
             i0_ff = Signal.like(pin_i0, name_suffix="_ff")

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index deda95916bd87a81c35d22004bbad3447ac2826e..c73c87e0aed276edecc720f9d0c54d172219187a 100644 (file)
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -156,7 +156,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
                     o_Q=q[bit]
                 )
 
-        def get_i_inverter(y, invert):
+        def get_ixor(y, invert):
             if invert is None:
                 return y
             else:
@@ -169,7 +169,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
                     )
                 return a
 
-        def get_o_inverter(a, invert):
+        def get_oxor(a, invert):
             if invert is None:
                 return a
             else:
@@ -184,28 +184,32 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
 
         if "i" in pin.dir:
             if pin.xdr < 2:
-                pin_i = get_i_inverter(pin.i, i_invert)
+                pin_i  = get_ixor(pin.i, i_invert)
             elif pin.xdr == 2:
-                pin_i0 = get_i_inverter(pin.i0, i_invert)
-                pin_i1 = get_i_inverter(pin.i1, i_invert)
+                pin_i0 = get_ixor(pin.i0, i_invert)
+                pin_i1 = get_ixor(pin.i1, i_invert)
         if "o" in pin.dir:
             if pin.xdr < 2:
-                pin_o = get_o_inverter(pin.o, o_invert)
+                pin_o  = get_oxor(pin.o, o_invert)
             elif pin.xdr == 2:
-                pin_o0 = get_o_inverter(pin.o0, o_invert)
-                pin_o1 = get_o_inverter(pin.o1, o_invert)
+                pin_o0 = get_oxor(pin.o0, o_invert)
+                pin_o1 = get_oxor(pin.o1, o_invert)
 
-        i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
-        o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
-        t = Signal(1,         name="{}_xdr_t".format(pin.name))
+        i = o = t = None
+        if "i" in pin.dir:
+            i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
+        if "o" in pin.dir:
+            o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
+        if pin.dir in ("oe", "io"):
+            t = Signal(1,         name="{}_xdr_t".format(pin.name))
 
         if pin.xdr == 0:
             if "i" in pin.dir:
-                m.d.comb += pin_i.eq(i)
+                i = pin_i
             if "o" in pin.dir:
-                m.d.comb += o.eq(pin_o)
+                o = pin_o
             if pin.dir in ("oe", "io"):
-                m.d.comb += t.eq(~pin.oe)
+                t = ~pin.oe
         elif pin.xdr == 1:
             if "i" in pin.dir:
                 get_dff(pin.i_clk, i, pin_i)

diff --git a/nmigen/vendor/xilinx_spartan6.py b/nmigen/vendor/xilinx_spartan6.py
index 5d83c22e7e1b45ade523f41b9028697e6bbdadef..7dae41028d8d45711aebfb713013827bbce384fb 100644 (file)
--- a/nmigen/vendor/xilinx_spartan6.py
+++ b/nmigen/vendor/xilinx_spartan6.py
@@ -167,7 +167,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
                     o_Q=q[bit]
                 )
 
-        def get_i_inverter(y, invert):
+        def get_ixor(y, invert):
             if invert is None:
                 return y
             else:
@@ -180,7 +180,7 @@ class XilinxSpartan6Platform(TemplatedPlatform):
                     )
                 return a
 
-        def get_o_inverter(a, invert):
+        def get_oxor(a, invert):
             if invert is None:
                 return a
             else:
@@ -195,28 +195,32 @@ class XilinxSpartan6Platform(TemplatedPlatform):
 
         if "i" in pin.dir:
             if pin.xdr < 2:
-                pin_i = get_i_inverter(pin.i, i_invert)
+                pin_i  = get_ixor(pin.i, i_invert)
             elif pin.xdr == 2:
-                pin_i0 = get_i_inverter(pin.i0, i_invert)
-                pin_i1 = get_i_inverter(pin.i1, i_invert)
+                pin_i0 = get_ixor(pin.i0, i_invert)
+                pin_i1 = get_ixor(pin.i1, i_invert)
         if "o" in pin.dir:
             if pin.xdr < 2:
-                pin_o = get_o_inverter(pin.o, o_invert)
+                pin_o  = get_oxor(pin.o, o_invert)
             elif pin.xdr == 2:
-                pin_o0 = get_o_inverter(pin.o0, o_invert)
-                pin_o1 = get_o_inverter(pin.o1, o_invert)
+                pin_o0 = get_oxor(pin.o0, o_invert)
+                pin_o1 = get_oxor(pin.o1, o_invert)
 
-        i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
-        o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
-        t = Signal(1,         name="{}_xdr_t".format(pin.name))
+        i = o = t = None
+        if "i" in pin.dir:
+            i = Signal(pin.width, name="{}_xdr_i".format(pin.name))
+        if "o" in pin.dir:
+            o = Signal(pin.width, name="{}_xdr_o".format(pin.name))
+        if pin.dir in ("oe", "io"):
+            t = Signal(1,         name="{}_xdr_t".format(pin.name))
 
         if pin.xdr == 0:
             if "i" in pin.dir:
-                m.d.comb += pin_i.eq(i)
+                i = pin_i
             if "o" in pin.dir:
-                m.d.comb += o.eq(pin_o)
+                o = pin_o
             if pin.dir in ("oe", "io"):
-                m.d.comb += t.eq(~pin.oe)
+                t = ~pin.oe
         elif pin.xdr == 1:
             if "i" in pin.dir:
                 get_dff(pin.i_clk, i, pin_i)