interconnect/wishbone: add FlipFlop to allow UpConverter to be used

Note: a test should be added for Converter and DownConverter/UpConverter should be cleaned up

diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index dc242f443185110975f3c4451c592445d8ba59cc..f76cdb4c4948c9d525fdfa01ac401c446a86fb94 100644 (file)
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -291,6 +291,15 @@ class DownConverter(Module):
             )
 
 
+@ResetInserter()
+@CEInserter()
+class FlipFlop(Module):
+    def __init__(self, *args, **kwargs):
+        self.d = Signal(*args, **kwargs)
+        self.q = Signal(*args, **kwargs)
+        self.sync += self.q.eq(self.d)
+
+
 class UpConverter(Module):
     """UpConverter