uint32_t mtilea;
uint32_t tile_split;
uint32_t stencil_tile_split;
- uint64_t stencil_offset;
struct radeon_surf_level level[RADEON_SURF_MAX_LEVEL];
struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVEL];
uint32_t tiling_index[RADEON_SURF_MAX_LEVEL];
surf_drm->mtilea = surf_ws->mtilea;
surf_drm->tile_split = surf_ws->tile_split;
surf_drm->stencil_tile_split = surf_ws->stencil_tile_split;
- surf_drm->stencil_offset = surf_ws->stencil_offset;
for (i = 0; i < RADEON_SURF_MAX_LEVEL; i++) {
surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->level[i]);
surf_ws->mtilea = surf_drm->mtilea;
surf_ws->tile_split = surf_drm->tile_split;
surf_ws->stencil_tile_split = surf_drm->stencil_tile_split;
- surf_ws->stencil_offset = surf_drm->stencil_offset;
surf_ws->macro_tile_index = cik_get_macro_tile_index(surf_ws);