targets: manual define of the SDRAM PHY no longer needed.

diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py
index 6e90ec47b976fc5290bdc2a21131d2fd03aa7597..74023f67cb6a14152c43dff279e01e75d09a831d 100755 (executable)
--- a/litex/boards/targets/kcu105.py
+++ b/litex/boards/targets/kcu105.py
@@ -67,7 +67,6 @@ class BaseSoC(SoCCore):
                 iodelay_clk_freq = 200e6,
                 cmd_latency      = 0)
             self.add_csr("ddrphy")
-            self.add_constant("USDDRPHY")
             self.add_constant("USDDRPHY_DEBUG")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,

diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index 216d7bb39052592fd6bf4be90e20b44150f2c1dc..49d8a6517a063d719e98500af9eecf39f3677e67 100755 (executable)
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -87,7 +87,6 @@ class BaseSoC(SoCCore):
                 platform.request("ddram"),
                 sys_clk_freq=sys_clk_freq)
             self.add_csr("ddrphy")
-            self.add_constant("ECP5DDRPHY")
             self.comb += self.crg.stop.eq(self.ddrphy.init.stop)
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,