#include "arch/arm/utility.hh"
#include "iris/detail/IrisCppAdapter.h"
#include "iris/detail/IrisObjects.h"
-#include "mem/fs_translating_port_proxy.hh"
#include "mem/se_translating_port_proxy.hh"
+#include "mem/translating_port_proxy.hh"
namespace Iris
{
assert(!physProxy && !virtProxy);
physProxy.reset(new PortProxy(_cpu->getSendFunctional(),
_cpu->cacheLineSize()));
- virtProxy.reset(new FSTranslatingPortProxy(tc));
+ virtProxy.reset(new TranslatingPortProxy(tc));
} else {
assert(!virtProxy);
virtProxy.reset(new SETranslatingPortProxy(this,
#include "cpu/thread_context.hh"
#include "debug/Loader.hh"
#include "kern/freebsd/events.hh"
-#include "mem/fs_translating_port_proxy.hh"
#include "mem/physical.hh"
#include "sim/stat_control.hh"
#include "kern/linux/events.hh"
#include "kern/linux/helpers.hh"
#include "kern/system_events.hh"
-#include "mem/fs_translating_port_proxy.hh"
#include "mem/physical.hh"
#include "sim/stat_control.hh"
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
-#include "mem/fs_translating_port_proxy.hh"
+#include "mem/port_proxy.hh"
#include "sim/system.hh"
namespace ArmISA
#include "cpu/thread_context.hh"
#include "dev/arm/fvp_base_pwr_ctrl.hh"
#include "dev/arm/gic_v2.hh"
-#include "mem/fs_translating_port_proxy.hh"
#include "mem/physical.hh"
using namespace std;
#include "config/the_isa.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
-#include "mem/fs_translating_port_proxy.hh"
#include "mem/packet.hh"
+#include "mem/port_proxy.hh"
#include "sim/core.hh"
#include "sim/faults.hh"
#include "sim/sim_exit.hh"
#include "cpu/base.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/thread_context.hh"
-#include "mem/fs_translating_port_proxy.hh"
+#include "mem/port_proxy.hh"
#include "sim/full_system.hh"
namespace ArmISA
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
-#include "mem/fs_translating_port_proxy.hh"
+#include "mem/port_proxy.hh"
#include "sim/system.hh"
using namespace MipsISA;
#include "base/logging.hh"
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
-#include "mem/fs_translating_port_proxy.hh"
#include "sim/serialize.hh"
using namespace MipsISA;
#include "arch/sparc/utility.hh"
#include "arch/sparc/faults.hh"
-#include "mem/fs_translating_port_proxy.hh"
+#include "mem/port_proxy.hh"
namespace SparcISA {
#include "base/trace.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
-#include "mem/fs_translating_port_proxy.hh"
+#include "mem/port_proxy.hh"
#include "sim/system.hh"
namespace X86ISA
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "debug/GDBAll.hh"
-#include "mem/fs_translating_port_proxy.hh"
#include "mem/port.hh"
-#include "mem/se_translating_port_proxy.hh"
+#include "mem/port_proxy.hh"
#include "sim/full_system.hh"
#include "sim/system.hh"
#include "cpu/profile.hh"
#include "cpu/quiesce_event.hh"
#include "cpu/thread_context.hh"
-#include "mem/fs_translating_port_proxy.hh"
#include "mem/se_translating_port_proxy.hh"
+#include "mem/translating_port_proxy.hh"
#include "params/BaseCPU.hh"
#include "sim/faults.hh"
#include "sim/full_system.hh"
#include "cpu/profile.hh"
#include "cpu/quiesce_event.hh"
#include "kern/kernel_stats.hh"
-#include "mem/fs_translating_port_proxy.hh"
#include "mem/port.hh"
#include "mem/port_proxy.hh"
#include "mem/se_translating_port_proxy.hh"
+#include "mem/translating_port_proxy.hh"
#include "sim/full_system.hh"
#include "sim/serialize.hh"
#include "sim/system.hh"
baseCpu->cacheLineSize());
assert(virtProxy == NULL);
- virtProxy = new FSTranslatingPortProxy(tc);
+ virtProxy = new TranslatingPortProxy(tc);
} else {
assert(virtProxy == NULL);
virtProxy = new SETranslatingPortProxy(
class Checkpoint;
-class FSTranslatingPortProxy;
-class SETranslatingPortProxy;
-
/**
* Struct for holding general thread state that is needed across CPU
* models. This includes things such as pointers to the process,
#include "debug/GIC.hh"
#include "dev/arm/gic_v3_cpu_interface.hh"
#include "dev/arm/gic_v3_distributor.hh"
-#include "mem/fs_translating_port_proxy.hh"
const AddrRange Gicv3Redistributor::GICR_IPRIORITYR(SGI_base + 0x0400,
SGI_base + 0x0420);
#include "arch/isa_traits.hh"
#include "config/the_isa.hh"
#include "cpu/thread_context.hh"
-#include "mem/fs_translating_port_proxy.hh"
+#include "mem/port_proxy.hh"
#include "sim/byteswap.hh"
#include "sim/system.hh"
Source('mem_delay.cc')
if env['TARGET_ISA'] != 'null':
- Source('fs_translating_port_proxy.cc')
+ Source('translating_port_proxy.cc')
Source('se_translating_port_proxy.cc')
Source('page_table.cc')
+++ /dev/null
-/*
- * Copyright (c) 2011,2013 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * @file
- * Port object definitions.
- */
-
-#include "mem/fs_translating_port_proxy.hh"
-
-#include "base/chunk_generator.hh"
-#include "cpu/base.hh"
-#include "cpu/thread_context.hh"
-#include "sim/system.hh"
-
-FSTranslatingPortProxy::FSTranslatingPortProxy(ThreadContext *tc) :
- PortProxy(tc->getCpuPtr()->getSendFunctional(),
- tc->getSystemPtr()->cacheLineSize()), _tc(tc),
- pageBytes(tc->getSystemPtr()->getPageBytes())
-{}
-
-bool
-FSTranslatingPortProxy::tryTLBsOnce(RequestPtr req, BaseTLB::Mode mode) const
-{
- BaseTLB *dtb = _tc->getDTBPtr();
- BaseTLB *itb = _tc->getDTBPtr();
- return dtb->translateFunctional(req, _tc, mode) == NoFault ||
- itb->translateFunctional(req, _tc, BaseTLB::Read) == NoFault;
-}
-
-bool
-FSTranslatingPortProxy::tryTLBs(RequestPtr req, BaseTLB::Mode mode) const
-{
- // If at first this doesn't succeed, try to fixup and translate again. If
- // it still fails, report failure.
- return tryTLBsOnce(req, mode) ||
- (fixupAddr(req->getVaddr(), mode) && tryTLBsOnce(req, mode));
-}
-
-bool
-FSTranslatingPortProxy::tryReadBlob(Addr addr, void *p, int size) const
-{
- for (ChunkGenerator gen(addr, size, pageBytes); !gen.done();
- gen.next())
- {
- auto req = std::make_shared<Request>(
- gen.addr(), gen.size(), 0, Request::funcMasterId, 0,
- _tc->contextId());
-
- if (!tryTLBs(req, BaseTLB::Read))
- return false;
-
- PortProxy::readBlobPhys(
- req->getPaddr(), req->getFlags(), p, gen.size());
-
- p = static_cast<uint8_t *>(p) + gen.size();
- }
- return true;
-}
-
-bool
-FSTranslatingPortProxy::tryWriteBlob(
- Addr addr, const void *p, int size) const
-{
- for (ChunkGenerator gen(addr, size, pageBytes); !gen.done();
- gen.next())
- {
- auto req = std::make_shared<Request>(
- gen.addr(), gen.size(), 0, Request::funcMasterId, 0,
- _tc->contextId());
-
- if (!tryTLBs(req, BaseTLB::Write))
- return false;
-
- PortProxy::writeBlobPhys(
- req->getPaddr(), req->getFlags(), p, gen.size());
- p = static_cast<const uint8_t *>(p) + gen.size();
- }
- return true;
-}
-
-bool
-FSTranslatingPortProxy::tryMemsetBlob(Addr address, uint8_t v, int size) const
-{
- for (ChunkGenerator gen(address, size, pageBytes); !gen.done();
- gen.next())
- {
- auto req = std::make_shared<Request>(
- gen.addr(), gen.size(), 0, Request::funcMasterId, 0,
- _tc->contextId());
-
- if (!tryTLBs(req, BaseTLB::Write))
- return false;
-
- PortProxy::memsetBlobPhys(
- req->getPaddr(), req->getFlags(), v, gen.size());
- }
- return true;
-}
+++ /dev/null
-/*
- * Copyright (c) 2011 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Copyright (c) 2006 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/**
- * @file
- * TranslatingPortProxy Object Declaration for FS.
- *
- * Port proxies are used when non structural entities need access to
- * the memory system. Proxy objects replace the previous
- * FunctionalPort, TranslatingPort and VirtualPort objects, which
- * provided the same functionality as the proxies, but were instances
- * of ports not corresponding to real structural ports of the
- * simulated system. Via the port proxies all the accesses go through
- * an actual port and thus are transparent to a potentially
- * distributed memory and automatically adhere to the memory map of
- * the system.
- */
-
-#ifndef __MEM_FS_TRANSLATING_PORT_PROXY_HH__
-#define __MEM_FS_TRANSLATING_PORT_PROXY_HH__
-
-#include "arch/generic/tlb.hh"
-#include "mem/port_proxy.hh"
-
-class ThreadContext;
-
-/**
- * This proxy attempts to translate virtual addresses using the TLBs. If it
- * fails, subclasses can override the fixupAddr virtual method to try to
- * recover, and then attempt the translation again. If it still fails then the
- * access as a whole fails.
- */
-class FSTranslatingPortProxy : public PortProxy
-{
- private:
- bool tryTLBsOnce(RequestPtr req, BaseTLB::Mode) const;
- bool tryTLBs(RequestPtr req, BaseTLB::Mode) const;
-
- protected:
- ThreadContext* _tc;
- const Addr pageBytes;
-
- virtual bool
- fixupAddr(Addr addr, BaseTLB::Mode mode) const
- {
- return false;
- }
-
- public:
-
- FSTranslatingPortProxy(ThreadContext* tc);
- ~FSTranslatingPortProxy() {}
-
- /** Version of tryReadblob that translates virt->phys and deals
- * with page boundries. */
- bool tryReadBlob(Addr addr, void *p, int size) const override;
-
- /** Version of tryWriteBlob that translates virt->phys and deals
- * with page boundries. */
- bool tryWriteBlob(Addr addr, const void *p, int size) const override;
-
- /**
- * Fill size bytes starting at addr with byte value val.
- */
- bool tryMemsetBlob(Addr address, uint8_t v, int size) const override;
-};
-
-#endif //__MEM_FS_TRANSLATING_PORT_PROXY_HH__
#include "sim/system.hh"
SETranslatingPortProxy::SETranslatingPortProxy(
- ThreadContext *tc, AllocType alloc)
- : FSTranslatingPortProxy(tc), allocating(alloc)
+ ThreadContext *tc, AllocType alloc) :
+ TranslatingPortProxy(tc), allocating(alloc)
{}
bool
#ifndef __MEM_SE_TRANSLATING_PORT_PROXY_HH__
#define __MEM_SE_TRANSLATING_PORT_PROXY_HH__
-#include "mem/fs_translating_port_proxy.hh"
+#include "mem/translating_port_proxy.hh"
-class SETranslatingPortProxy : public FSTranslatingPortProxy
+class SETranslatingPortProxy : public TranslatingPortProxy
{
public:
--- /dev/null
+/*
+ * Copyright (c) 2011,2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file
+ * Port object definitions.
+ */
+
+#include "mem/translating_port_proxy.hh"
+
+#include "base/chunk_generator.hh"
+#include "cpu/base.hh"
+#include "cpu/thread_context.hh"
+#include "sim/system.hh"
+
+TranslatingPortProxy::TranslatingPortProxy(ThreadContext *tc) :
+ PortProxy(tc->getCpuPtr()->getSendFunctional(),
+ tc->getSystemPtr()->cacheLineSize()), _tc(tc),
+ pageBytes(tc->getSystemPtr()->getPageBytes())
+{}
+
+bool
+TranslatingPortProxy::tryTLBsOnce(RequestPtr req, BaseTLB::Mode mode) const
+{
+ BaseTLB *dtb = _tc->getDTBPtr();
+ BaseTLB *itb = _tc->getDTBPtr();
+ return dtb->translateFunctional(req, _tc, mode) == NoFault ||
+ itb->translateFunctional(req, _tc, BaseTLB::Read) == NoFault;
+}
+
+bool
+TranslatingPortProxy::tryTLBs(RequestPtr req, BaseTLB::Mode mode) const
+{
+ // If at first this doesn't succeed, try to fixup and translate again. If
+ // it still fails, report failure.
+ return tryTLBsOnce(req, mode) ||
+ (fixupAddr(req->getVaddr(), mode) && tryTLBsOnce(req, mode));
+}
+
+bool
+TranslatingPortProxy::tryReadBlob(Addr addr, void *p, int size) const
+{
+ for (ChunkGenerator gen(addr, size, pageBytes); !gen.done();
+ gen.next())
+ {
+ auto req = std::make_shared<Request>(
+ gen.addr(), gen.size(), 0, Request::funcMasterId, 0,
+ _tc->contextId());
+
+ if (!tryTLBs(req, BaseTLB::Read))
+ return false;
+
+ PortProxy::readBlobPhys(
+ req->getPaddr(), req->getFlags(), p, gen.size());
+
+ p = static_cast<uint8_t *>(p) + gen.size();
+ }
+ return true;
+}
+
+bool
+TranslatingPortProxy::tryWriteBlob(
+ Addr addr, const void *p, int size) const
+{
+ for (ChunkGenerator gen(addr, size, pageBytes); !gen.done();
+ gen.next())
+ {
+ auto req = std::make_shared<Request>(
+ gen.addr(), gen.size(), 0, Request::funcMasterId, 0,
+ _tc->contextId());
+
+ if (!tryTLBs(req, BaseTLB::Write))
+ return false;
+
+ PortProxy::writeBlobPhys(
+ req->getPaddr(), req->getFlags(), p, gen.size());
+ p = static_cast<const uint8_t *>(p) + gen.size();
+ }
+ return true;
+}
+
+bool
+TranslatingPortProxy::tryMemsetBlob(Addr address, uint8_t v, int size) const
+{
+ for (ChunkGenerator gen(address, size, pageBytes); !gen.done();
+ gen.next())
+ {
+ auto req = std::make_shared<Request>(
+ gen.addr(), gen.size(), 0, Request::funcMasterId, 0,
+ _tc->contextId());
+
+ if (!tryTLBs(req, BaseTLB::Write))
+ return false;
+
+ PortProxy::memsetBlobPhys(
+ req->getPaddr(), req->getFlags(), v, gen.size());
+ }
+ return true;
+}
--- /dev/null
+/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MEM_TRANSLATING_PORT_PROXY_HH__
+#define __MEM_TRANSLATING_PORT_PROXY_HH__
+
+#include "arch/generic/tlb.hh"
+#include "mem/port_proxy.hh"
+
+class ThreadContext;
+
+/**
+ * This proxy attempts to translate virtual addresses using the TLBs. If it
+ * fails, subclasses can override the fixupAddr virtual method to try to
+ * recover, and then attempt the translation again. If it still fails then the
+ * access as a whole fails.
+ */
+class TranslatingPortProxy : public PortProxy
+{
+ private:
+ bool tryTLBsOnce(RequestPtr req, BaseTLB::Mode) const;
+ bool tryTLBs(RequestPtr req, BaseTLB::Mode) const;
+
+ protected:
+ ThreadContext* _tc;
+ const Addr pageBytes;
+
+ virtual bool
+ fixupAddr(Addr addr, BaseTLB::Mode mode) const
+ {
+ return false;
+ }
+
+ public:
+
+ TranslatingPortProxy(ThreadContext* tc);
+
+ /** Version of tryReadblob that translates virt->phys and deals
+ * with page boundries. */
+ bool tryReadBlob(Addr addr, void *p, int size) const override;
+
+ /** Version of tryWriteBlob that translates virt->phys and deals
+ * with page boundries. */
+ bool tryWriteBlob(Addr addr, const void *p, int size) const override;
+
+ /**
+ * Fill size bytes starting at addr with byte value val.
+ */
+ bool tryMemsetBlob(Addr address, uint8_t v, int size) const override;
+};
+
+#endif //__MEM_TRANSLATING_PORT_PROXY_HH__
#include <memory>
#include "cpu/thread_context.hh"
-#include "mem/fs_translating_port_proxy.hh"
+#include "mem/port_proxy.hh"
class Arguments
{
#ifndef __SIM_VPTR_HH__
#define __SIM_VPTR_HH__
-#include "mem/fs_translating_port_proxy.hh"
+#include "mem/port_proxy.hh"
class ThreadContext;
projects / gem5.git / commitdiff