(no commit message)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 490e1efdfb0e86d88af46947670aa0cc2b9a23ab..25f797934d9953bfed481fb4199176244a47c6ab 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -207,11 +207,6 @@ LRu and CTR-test modes are where SVP64 Branches subtly differ from
 Scalar v3.0B Branches. `bclr` for example will always update LR, whereas
 `sv.bclr/lru` will only update LR if the branch succeeds.
 
-*Programmer's Note: when using `bclr` with `LRu=1,LK=0` in Horizontal-First Mode,
-LR's value will be unconditionally overwritten after the first element,
-such that for execution (testing) of the second element, LR
-has the value `CIA+8`. This is covered in the `bclrl` example, below.
-
 Of special interest is that when using ALL Mode (Great Big AND
 of all Condition Tests), if `VL=0`,
 which is rare but can occur in Data-Dependent Modes, the Branch
@@ -337,14 +332,30 @@ multiple CR Fields covered by multiple predicate bits, would
 do the exact same thing.*
 
 ## Link Register Update
-  - When LRu=0,LK=1, Link Register is updated unconditionally.
-  - When LRu=1,LK=1, Link Register will
+
+For a Scalar Branch, unconditional updating of the Link Register
+LR is useful and practical. However, if a loop of CR Fields is
+tested, unconditional updating of LR becomes problematic.
+
+For example when using `bclr` with `LRu=1,LK=0` in Horizontal-First Mode,
+LR's value will be unconditionally overwritten after the first element,
+such that for execution (testing) of the second element, LR
+has the value `CIA+8`. This is covered in the `bclrl` example, in
+a later section.
+
+The addition of a LRu bit modifies behaviour in conjunction
+with LK, as follows:
+
+* `sv.bc` When LRu=0,LK=0, Link Register is not updated
+* `sv.bcl` When LRu=0,LK=1, Link Register is updated unconditionally
+* `sv.bcl/lru` When LRu=1,LK=1, Link Register will
   only be updated if the Branch Condition succeeds.
-  - When LRu=1,LK=0, Link Register will only be updated if
+* `sv.bc/lru` When LRu=1,LK=0, Link Register will only be updated if
   the Branch Condition fails.
-  - This avoids
-  destruction of LR during loops (particularly Vertical-First
-  ones).
+
+This avoids
+destruction of LR during loops (particularly Vertical-First
+ones).
 
 ## CTR-test