remove not needed top module

diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v
index 75149d8ba2711a020fb9924ac886099ecb758929..c6446825342680e9b587ad1453b53aad4cbff0a4 100644 (file)
--- a/tests/xilinx/tribuf.v
+++ b/tests/xilinx/tribuf.v
@@ -6,18 +6,3 @@ module tristate (en, i, o);
     always @(en or i)
                o <= (en)? i : 1'bZ;
 endmodule
-
-
-module top (
-input en,
-input a,
-output b
-);
-
-tristate u_tri (
-        .en (en ),
-        .i (a ),
-        .o (b )
-    );
-
-endmodule

diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys
index 696be2620cb246024f94c4aadbecb41eb02fd99f..c9cfb85468e313d7f7c9a6948592da13cd8937fb 100644 (file)
--- a/tests/xilinx/tribuf.ys
+++ b/tests/xilinx/tribuf.ys
@@ -1,12 +1,12 @@
 read_verilog tribuf.v
-hierarchy -top top
+hierarchy -top tristate
 proc
 tribuf
 flatten
 synth
 equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd tristate # Constrain all select calls below inside the top module
 # TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D