In SV given the percentage of operations that also involve initislisation to 0.0 or 1.0 into subvector elements the decision was made to include those:
swizzle = get_swizzle_immed() # 12 bits
- remap = (swizzle >> 3*s) & 0b111
- if remap < 4:
- sm = id*SUBVL + remap
- ireg[rd+s] <= ireg[rs1+sm]
- elif remap == 4:
- ireg[rd+s] <= 0.0
- elif remap == 5:
- ireg[rd+s] <= 1.0
+ for (s = 0; s < SUBVL; s++)
+ remap = (swizzle >> 3*s) & 0b111
+ if remap < 4:
+ sm = id*SUBVL + remap
+ ireg[rd+s] <= ireg[rs1+sm]
+ elif remap == 4:
+ ireg[rd+s] <= 0.0
+ elif remap == 5:
+ ireg[rd+s] <= 1.0
Note that a value of 6 (and 7) will leave the target subvector element untouched. This is equivalent to a predicate mask which is built-in, in immediate form, into the [[sv/mv.swizzle]] operation. mv.swizzle is rare in that it is one of the few instructions needed to be added that are never going to be part of a Scalar ISA. Even in High Performance Compute workloads it is unusual: it is only because SV is targetted at 3D and Video that it is being considered.