Miscellaneous minor issues flagged by cppcheck.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
ins.src[is_read ? 0 : 1] = addr;
/* TODO: What is this? It looks superficially like a shift << 5, but
- * arg_1 doesn't take a shift Should it be E0 or A0? */
- if (indirect_offset)
- ins.load_store.arg_1 |= 0xE0;
-
- /* We also need to emit the indirect offset */
+ * arg_1 doesn't take a shift Should it be E0 or A0? We also need the
+ * indirect offset. */
- if (indirect_offset)
+ if (indirect_offset) {
+ ins.load_store.arg_1 |= 0xE0;
ins.src[is_read ? 1 : 2] = nir_src_index(ctx, indirect_offset);
- else
+ } else {
ins.load_store.arg_2 = 0x7E;
+ }
/* TODO: Bounds check */
reg = nir_dest_index(ctx, &instr->dest);
assert(ctx->is_blend);
- midgard_instruction ins = m_ld_color_buffer_8(reg, 0);
- emit_mir_instruction(ctx, ins);
+ midgard_instruction ld = m_ld_color_buffer_8(reg, 0);
+ emit_mir_instruction(ctx, ld);
break;
case nir_intrinsic_load_blend_const_color_rgba: {
fprintf(stderr, "shader%d - %s shader: "
"%u inst, %u bundles, %u quadwords, "
"%u registers, %u threads, %u loops, "
- "%d:%d spills:fills\n",
+ "%u:%u spills:fills\n",
SHADER_DB_COUNT++,
gl_shader_stage_name(ctx->stage),
nr_ins, nr_bundles, ctx->quadword_count,
/* TODO: Integers */
unsigned component = (v.swizzle >> (2*masked_component)) & 3;
- bool upper = false; /* TODO */
midgard_scalar_alu_src s = { 0 };
if (s.full)
s.component = component << 1;
- else
+ else {
+ bool upper = false; /* TODO */
s.component = component + (upper << 2);
+ }
if (is_int) {
/* TODO */
void
mir_print_block(midgard_block *block)
{
- printf("block%d: {\n", block->source_id);
+ printf("block%u: {\n", block->source_id);
if (block->is_scheduled) {
mir_foreach_bundle_in_block(block, bundle) {
if (block->nr_successors) {
printf(" -> ");
for (unsigned i = 0; i < block->nr_successors; ++i) {
- printf("block%d%s", block->successors[i]->source_id,
+ printf("block%u%s", block->successors[i]->source_id,
(i + 1) != block->nr_successors ? ", " : "");
}
}
printf(" from { ");
mir_foreach_predecessor(block, pred)
- printf("block%d ", pred->source_id);
+ printf("block%u ", pred->source_id);
printf("}");
printf("\n\n");
unsigned pipeline_count)
{
midgard_instruction *ins = bundle->instructions[i];
- unsigned dest = ins->dest;
/* We could be pipelining a register, so we need to make sure that all
* of the components read in this bundle are written in this bundle,
/* We're only live in this bundle -- pipeline! */
- mir_rewrite_index(ctx, dest, SSA_FIXED_REGISTER(24 + pipeline_count));
+ mir_rewrite_index(ctx, node, SSA_FIXED_REGISTER(24 + pipeline_count));
return true;
}
/* Simultaneously we scan for the set of dependencies */
size_t sz = sizeof(BITSET_WORD) * BITSET_WORDS(node_count);
- BITSET_WORD *dependencies = alloca(sz);
+ BITSET_WORD *dependencies = calloc(1, sz);
memset(dependencies, 0, sz);
+ bool success = false;
+
for (unsigned i = 0; i < count; ++i) {
midgard_instruction *ins = bundle[i];
/* Requirement 2 */
if (ins->unit == UNIT_VLUT)
- return false;
+ goto done;
}
/* Requirement 1 */
if ((r0_written_mask & 0xF) != 0xF)
- return false;
+ goto done;
/* Requirement 3 */
unsigned dest = bundle[i]->dest;
if (dest < node_count && BITSET_TEST(dependencies, dest))
- return false;
+ goto done;
}
/* Otherwise, we're good to go */
- return true;
+ success = true;
+
+done:
+ free(dependencies);
+ return success;
}
/* Helpers for scheudling */