back.pysim: handle non-driven, non-port signals.

Fixes #20.

diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py
index fa90461d92087eb708f8a7e182ef3adb3ff55657..1278923ba67894b5ca153b555fe34c383238f712 100644 (file)
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@@ -90,6 +90,9 @@ class _RHSValueCompiler(_ValueCompiler):
     def on_Signal(self, value):
         if self.sensitivity is not None:
             self.sensitivity.add(value)
+        if value not in self.signal_slots:
+            # A signal that is neither driven nor a port always remains at its reset state.
+            return lambda state: value.reset
         value_slot = self.signal_slots[value]
         if self.signal_mode == "rhs":
             return lambda state: state.curr[value_slot]
@@ -551,7 +554,8 @@ class Simulator:
             funclet = compiler(statements)
 
             def add_funclet(signal, funclet):
-                self._funclets[self._signal_slots[signal]].add(funclet)
+                if signal in self._signal_slots:
+                    self._funclets[self._signal_slots[signal]].add(funclet)
 
             for signal in compiler.sensitivity:
                 add_funclet(signal, funclet)

diff --git a/nmigen/test/test_sim.py b/nmigen/test/test_sim.py
index 5b7722286db2835b3694b25f7e1630b8a0c514ac..a8782258896e96fde5c2aa6bb0c972b05994fef7 100644 (file)
--- a/nmigen/test/test_sim.py
+++ b/nmigen/test/test_sim.py
@@ -531,6 +531,20 @@ class SimulatorIntegrationTestCase(FHDLTestCase):
             sim.add_clock(1e-6)
             sim.add_process(process)
 
+    def test_memory_read_only(self):
+        self.m = Module()
+        self.memory = Memory(width=8, depth=4, init=[0xaa, 0x55])
+        self.m.submodules.rdport = self.rdport = self.memory.read_port()
+        with self.assertSimulation(self.m) as sim:
+            def process():
+                self.assertEqual((yield self.rdport.data), 0xaa)
+                yield self.rdport.addr.eq(1)
+                yield
+                yield
+                self.assertEqual((yield self.rdport.data), 0x55)
+            sim.add_clock(1e-6)
+            sim.add_sync_process(process)
+
     def test_wrong_not_run(self):
         with self.assertWarns(UserWarning,
                 msg="Simulation created, but not run"):