fastmodel: Handle "special" vector regs without calling into IRIS.

These registers don't have an architectural equivalent, but they may
need to be accessed by generic code, for instance the code that
checkpoints a thread context.

Change-Id: I4a18f44f2c09e379a4629c8e3eb8070b5c01918e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23784
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/fastmodel/iris/arm/thread_context.cc b/src/arch/arm/fastmodel/iris/arm/thread_context.cc
index c48ade817ca76c107dd6802c13b744cb019c4038..4ef8794885a81a37ffec3f89d41d802e3a45ffde 100644 (file)
--- a/src/arch/arm/fastmodel/iris/arm/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/arm/thread_context.cc
@@ -190,6 +190,11 @@ const ArmISA::VecRegContainer &
 ArmThreadContext::readVecReg(const RegId &reg_id) const
 {
     const RegIndex idx = reg_id.index();
+    // Ignore accesses to registers which aren't architected. gem5 defines a
+    // few extra registers which it uses internally in the implementation of
+    // some instructions.
+    if (idx >= vecRegIds.size())
+        return vecRegs.at(idx);
     ArmISA::VecRegContainer &reg = vecRegs.at(idx);
 
     iris::ResourceReadResult result;