Re: [libre-riscv-dev] cache SRAM organisation

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+Subject: Re: [libre-riscv-dev] cache SRAM organisation
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+(Sorry send to early)
+
+
+> .In theory on a single port SRAM
+
+In theory on a single port SRAM the write data input and the Q data output =
+could be on opposite sides of the block but I will make sure that these pin=
+s are on the same side of the block and close together so you don't need mu=
+ch wire to connect a pass-through MUX.
+
+greets,
+Staf.
+
+
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