--- /dev/null
+// This test checks that we correctly elaborate interfaces in modules, even if they are loaded on
+// demand. The "ondemand" module is defined in ondemand.sv in this directory and will be read as
+// part of the hierarchy pass.
+
+interface iface;
+ logic [7:0] x;
+ logic [7:0] y;
+endinterface
+
+module dut (input logic [7:0] x, output logic [7:0] y);
+ iface intf();
+ assign intf.x = x;
+ assign y = intf.y;
+
+ ondemand u(.intf);
+endmodule
+
+module ref (input logic [7:0] x, output logic [7:0] y);
+ assign y = ~x;
+endmodule
--- /dev/null
+read_verilog -sv load_and_derive.sv
+hierarchy -libdir . -check
+flatten
+equiv_make ref dut equiv
+equiv_simple
+equiv_status -assert
--- /dev/null
+// This is used by the load_and_derive test.
+
+module ondemand (iface intf);
+ assign intf.y = ~intf.x;
+endmodule
#/bin/bash -e
-
-
./runone.sh svinterface1
./runone.sh svinterface_at_top
+
+./run_simple.sh load_and_derive
--- /dev/null
+#!/bin/bash
+
+# Run a simple test with a .ys file
+
+if [ $# != 1 ]; then
+ echo >&2 "Expected 1 argument"
+ exit 1
+fi
+
+echo -n "Test: $1 ->"
+../../yosys $1.ys >$1.log_stdout 2>$1.log_stderr || {
+ echo "ERROR!"
+ exit 1
+}
+echo "ok"