Merge remote-tracking branch 'origin/master' into xaig

diff --cc CHANGELOG
index f7a6e975872e04429200be7882098709b1656b55,496a521be6cf6221d454a5e22f45918b0b7ec882..192fc5a8dfccdfeb1e7cf844deb2a8d33078f9c7
--- 1/CHANGELOG
--- 2/CHANGELOG
+++ b/CHANGELOG
@@@ -16,14 -16,10 +16,15 @@@ Yosys 0.8 .. Yosys 0.8-de
      - Added "gate2lut.v" techmap rule
      - Added "rename -src"
      - Added "equiv_opt" pass
 +    - Added "shregmap -tech xilinx"
      - Added "read_aiger" frontend
 +    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 +    - Added "synth_xilinx -abc9" (experimental)
 +    - Added "synth_ice40 -abc9" (experimental)
 +    - Added "synth -abc9" (experimental)
      - Extended "muxcover -mux{4,8,16}=<cost>"
 -    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
 +    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
+     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
  
  
  Yosys 0.7 .. Yosys 0.8