-Olivier Hainque <hainque@adacore.com>
+2017-08-06 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.c (ix86_stack_protect_guard): Generate
+ memory reference to a SSP offset in TLS address space.
+ (ix86_print_operand) <case '@'>: Remove.
+ (ix86_print_operand_punct_valid_p): Remove '@' code.
+ * config/i386/i386.md (unspec): Remove UNSPEC_SP_TLS_SET and
+ UNSPEC_SP_TLS_TEST.
+ (stack_tls_protect_set_<mode>): Remove.
+ (stack_protect_set): Do not call gen_stack_tls_protect_set_<mode>.
+ (stack_tls_protect_test_<mode>): Remove.
+ (stack_protect_test): Do not call gen_stack_tls_protect_test_<mode>.
+
+2017-08-07 Olivier Hainque <hainque@adacore.com>
PR target/81755
* config/vxworksae.h (VXWORKS_HAVE_TLS): Define.
+ -- print a branch hint as 'cs' or 'ds' prefix
; -- print a semicolon (after prefixes due to bug in older gas).
~ -- print "i" if TARGET_AVX2, "f" otherwise.
- @ -- print a segment register of thread base pointer load
^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
! -- print MPX prefix for jxx/call/ret instructions if required.
*/
#endif
return;
- case '@':
- if (ASSEMBLER_DIALECT == ASM_ATT)
- putc ('%', file);
-
- /* The kernel uses a different segment register for performance
- reasons; a system call would not have to trash the userspace
- segment register, which would be expensive. */
- if (TARGET_64BIT && ix86_cmodel != CM_KERNEL)
- fputs ("fs", file);
- else
- fputs ("gs", file);
- return;
-
case '~':
putc (TARGET_AVX2 ? 'i' : 'f', file);
return;
static bool
ix86_print_operand_punct_valid_p (unsigned char code)
{
- return (code == '@' || code == '*' || code == '+' || code == '&'
- || code == ';' || code == '~' || code == '^' || code == '!');
+ return (code == '*' || code == '+' || code == '&' || code == ';'
+ || code == '~' || code == '^' || code == '!');
}
\f
/* Print a memory operand whose address is ADDR. */
}
#ifdef TARGET_THREAD_SSP_OFFSET
-/* If using TLS guards, don't waste time creating and expanding
- __stack_chk_guard decl and MEM as we are going to ignore it. */
static tree
ix86_stack_protect_guard (void)
{
if (TARGET_SSP_TLS_GUARD)
- return NULL_TREE;
+ {
+ tree type_node = lang_hooks.types.type_for_mode (ptr_mode, 1);
+ addr_space_t as = DEFAULT_TLS_SEG_REG;
+
+ /* The kernel uses a different segment register for performance
+ reasons; a system call would not have to trash the userspace
+ segment register, which would be expensive. */
+ if (ix86_cmodel == CM_KERNEL)
+ as = ADDR_SPACE_SEG_GS;
+
+ int qual = ENCODE_QUAL_ADDR_SPACE (as);
+
+ tree type = build_qualified_type (type_node, qual);
+ tree asptrtype = build_pointer_type (type);
+ tree sspoff = build_int_cst (asptrtype, TARGET_THREAD_SSP_OFFSET);
+
+ tree t = build2 (MEM_REF, asptrtype, sspoff,
+ build_int_cst (asptrtype, 0));
+ return t;
+ }
+
return default_stack_protect_guard ();
}
#endif
;; + -- print a branch hint as 'cs' or 'ds' prefix
;; ; -- print a semicolon (after prefixes due to bug in older gas).
;; ~ -- print "i" if TARGET_AVX2, "f" otherwise.
-;; @ -- print a segment register of thread base pointer load
;; ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
;; ! -- print MPX prefix for jxx/call/ret instructions if required.
;; SSP patterns
UNSPEC_SP_SET
UNSPEC_SP_TEST
- UNSPEC_SP_TLS_SET
- UNSPEC_SP_TLS_TEST
;; For ROUND support
UNSPEC_ROUND
{
rtx (*insn)(rtx, rtx);
-#ifdef TARGET_THREAD_SSP_OFFSET
- operands[1] = GEN_INT (TARGET_THREAD_SSP_OFFSET);
- insn = (TARGET_LP64
- ? gen_stack_tls_protect_set_di
- : gen_stack_tls_protect_set_si);
-#else
insn = (TARGET_LP64
? gen_stack_protect_set_di
: gen_stack_protect_set_si);
-#endif
emit_insn (insn (operands[0], operands[1]));
DONE;
"mov{<imodesuffix>}\t{%1, %2|%2, %1}\;mov{<imodesuffix>}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
[(set_attr "type" "multi")])
-(define_insn "stack_tls_protect_set_<mode>"
- [(set (match_operand:PTR 0 "memory_operand" "=m")
- (unspec:PTR [(match_operand:PTR 1 "const_int_operand" "i")]
- UNSPEC_SP_TLS_SET))
- (set (match_scratch:PTR 2 "=&r") (const_int 0))
- (clobber (reg:CC FLAGS_REG))]
- ""
- "mov{<imodesuffix>}\t{%@:%P1, %2|%2, <iptrsize> PTR %@:%P1}\;mov{<imodesuffix>}\t{%2, %0|%0, %2}\;xor{l}\t%k2, %k2"
- [(set_attr "type" "multi")])
-
(define_expand "stack_protect_test"
[(match_operand 0 "memory_operand")
(match_operand 1 "memory_operand")
rtx (*insn)(rtx, rtx, rtx);
-#ifdef TARGET_THREAD_SSP_OFFSET
- operands[1] = GEN_INT (TARGET_THREAD_SSP_OFFSET);
- insn = (TARGET_LP64
- ? gen_stack_tls_protect_test_di
- : gen_stack_tls_protect_test_si);
-#else
insn = (TARGET_LP64
? gen_stack_protect_test_di
: gen_stack_protect_test_si);
-#endif
emit_insn (insn (flags, operands[0], operands[1]));
"mov{<imodesuffix>}\t{%1, %3|%3, %1}\;xor{<imodesuffix>}\t{%2, %3|%3, %2}"
[(set_attr "type" "multi")])
-(define_insn "stack_tls_protect_test_<mode>"
- [(set (match_operand:CCZ 0 "flags_reg_operand")
- (unspec:CCZ [(match_operand:PTR 1 "memory_operand" "m")
- (match_operand:PTR 2 "const_int_operand" "i")]
- UNSPEC_SP_TLS_TEST))
- (clobber (match_scratch:PTR 3 "=r"))]
- ""
- "mov{<imodesuffix>}\t{%1, %3|%3, %1}\;xor{<imodesuffix>}\t{%@:%P2, %3|%3, <iptrsize> PTR %@:%P2}"
- [(set_attr "type" "multi")])
-
(define_insn "sse4_2_crc32<mode>"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI
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