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diff --git a/SEP-210803722-Libre-SOC-8-core.mdwn b/SEP-210803722-Libre-SOC-8-core.mdwn
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--- a/SEP-210803722-Libre-SOC-8-core.mdwn
+++ b/SEP-210803722-Libre-SOC-8-core.mdwn
@@ -234,7 +234,9 @@ Summary of why our work is pertinent to Call HORIZON-CL4-2021-DIGITAL-EMERGING-0
 * Targeted applications: We are developing a general-purpose Hybrid Architecture suitable for 3D, Video, Digital Signal Processing, Cryptographic applications, AI and many more.  As it is general-purpose it covers all these areas.  However in certain areas "specialist" instructions are needed (particularly 3D) and we seek additional funding to complete them.  This includes Helix's high-accuracy GPS application which qualifies as a step-improvement in "Sensor fusion".
 * Hardware-software co-design and Libre/Open Hardware-Software: as all participants are trained as Software Engineers, we inherently and automatically bring Software Engineering practices and techniques to Hardware design, and consequently achieve a far greater effectiveness and flexibility. Additionally, all participants are long-term contributors to Libre/Open Software and Hardware Projects. This shall continue throughout this Grant proposal.  The involvement of RED Semiconductor Ltd brings further semiconductor hardware experience, bringing balance to the overall team.
 * Moore's Law and changing Economics: as a general-purpose Cray-style Vector Supercomputer ISA, what we are designing may deploy either "Fast and Narrow" back-end (internal) micro-architecture, or "Slow and Wide": huge numbers of SIMD ALUs running at a much slower clock rate.  The beauty and elegance of a Vector ISA is that, unlike SIMD ISAs such as AVX-512, NEON and to a partial extend SVE2, is that the programmer doesn't need to know about the internal micro-architecture, but their programs achieve the same throughput, even on larger geometries.
-* Hardware-based security: We consider it deeply unwise to follow the false practice of "adding more complexity to achieve more security".  Security is achieved through simplicity and transparency.  Simplicity: we studied historic Supercomputer designs dating back to 1965 (CDC 6600) where pure pragmatism required simpler and more elegant designs.  Transparency: Fully Libre/Open designs that customers can themselves verify by running Formal Correctness Proofs (where those tools are also Libre/Open Source). Fully Libre/Open VLSI toolchains and Cell Libraries (no possibility of insertion of spying at the Silicon level). "Tripwires" embedded into the silicon to gauge area-local EMF "Signatures". Additionally, we already have work underway into Out-of-Order Execution and seek to explore Speculative Execution Mitigation techniques at the hardware level, to increase security. These are practical achievable demonstrable ways to achieve Hardware-based trust.
+* Hardware-based security: We consider it deeply unwise to follow the false practice of "adding more complexity to achieve more security".  Security is achieved through simplicity and transparency.  Simplicity: we studied historic Supercomputer designs dating back to 1965 (CDC 6600) where pure pragmatism required simpler and more elegant designs,
+and with Mitch Alsup's help learned how to bring them up-to-date.
+Transparency: Fully Libre/Open designs that customers can themselves verify by running Formal Correctness Proofs (where those tools are also Libre/Open Source). Fully Libre/Open VLSI toolchains and Cell Libraries (no possibility of insertion of spying at the Silicon level). "Tripwires" embedded into the silicon to gauge area-local EMF "Signatures". Additionally, we already have work underway into Out-of-Order Execution and seek to explore Speculative Execution Mitigation techniques at the hardware level, to increase security. These are practical achievable demonstrable ways to achieve Hardware-based trust.
 * Security and Safety-critical Guidelines: Due to our overall approach, although potentially inherently achievable by others utilising our work as the basis for ongoing Research, the main participants consider it out of scope due to practical time constraints.  Security Certification typically takes 5 to 7 years: The scope of this project is only 3.  NLnet however may fund work that does indeed take into account these criteria.
 * ASIC (Chip) prototyping: We are developing RTL including High-Level (core designs) as well as Low-Level (Cell Libraries).  Nobody in any European Company will use a Cell Library if it has not been demonstrated as Silicon-Proven.  As we already did with the 180nm ASIC, the best way to prove that a Cell Library (and an innovative approach - using Libre/Open VLSI toolchains) works is to do an actual ASIC.