Expose the BTI BTYPE more explicitly in the registers

Augment the register description XML to expose the BTI BTYPE field contained
in the CPSR register. It will be displayed like so:

cpsr           0x60001000          [ EL=0 BTYPE=0 SSBS C Z ]

diff --git a/gdb/features/aarch64-core.c b/gdb/features/aarch64-core.c
index a080a641c45f55cb020f85da5411475c1d13ac44..bb707173be6d2145e8032397a7de82bd3952a4ac 100644 (file)
--- a/gdb/features/aarch64-core.c
+++ b/gdb/features/aarch64-core.c
@@ -18,6 +18,7 @@ create_feature_aarch64_core (struct target_desc *result, long regnum)
   tdesc_add_flag (type_with_fields, 7, "I");
   tdesc_add_flag (type_with_fields, 8, "A");
   tdesc_add_flag (type_with_fields, 9, "D");
+  tdesc_add_bitfield (type_with_fields, "BTYPE", 10, 11);
   tdesc_add_flag (type_with_fields, 12, "SSBS");
   tdesc_add_flag (type_with_fields, 20, "IL");
   tdesc_add_flag (type_with_fields, 21, "SS");

diff --git a/gdb/features/aarch64-core.xml b/gdb/features/aarch64-core.xml
index d63456956fdf637557751edfe7a0bd78509aae63..a328ede508c6ee8344f827092726f78d33ab7e9b 100644 (file)
--- a/gdb/features/aarch64-core.xml
+++ b/gdb/features/aarch64-core.xml
@@ -61,6 +61,9 @@
     <!-- Debug exception mask.  -->
     <field name="D" start="9" end="9"/>
 
+    <!-- ARMv8.5-A: Branch Target Identification BTYPE.  -->
+    <field name="BTYPE" start="10" end="11"/>
+
     <!-- ARMv8.0-A: Speculative Store Bypass.  -->
     <field name="SSBS" start="12" end="12"/>