Minor fixes in abc build instructions and abc pass

diff --git a/Makefile b/Makefile
index 4384de5fe651d3cc1f8b3a6e1f61a11e1ba4cca4..c0a36494d9aa18dc0528132141a8c6dc00e20e71 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -86,7 +86,7 @@ yosys-svgviewer: libs/svgviewer/*.h libs/svgviewer/*.cpp
 
 abc:
        test -d abc || hg clone https://bitbucket.org/alanmi/abc abc
-       cd abc && hg pull && make
+       cd abc && hg pull && hg update && make
        cp abc/abc yosys-abc
 
 test: yosys

diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index c1f9eb2d90aa8dcd28b050735da4f3d6e0e38bf6..41104ee998642c4a2b488c76c093b501c8365202 100644 (file)
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -457,21 +457,21 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
                int buffer_pos = 0;
                if (!liberty_file.empty())
                        buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
-                                       "%s -c 'read_verilog %s/input.v; read_liberty %s; map; ",
+                                       "%s -s -c 'read_verilog %s/input.v; read_liberty %s; map; ",
                                        exe_file.c_str(), tempdir_name, liberty_file.c_str());
                else
                if (!script_file.empty())
                        buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
-                                       "%s -c 'read_verilog %s/input.v; source %s; ",
+                                       "%s -s -c 'read_verilog %s/input.v; source %s; ",
                                        exe_file.c_str(), tempdir_name, script_file.c_str());
                else
                if (lut_mode)
                        buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
-                                       "%s -c 'read_verilog %s/input.v; read_lut %s/lutdefs.txt; if; ",
+                                       "%s -s -c 'read_verilog %s/input.v; read_lut %s/lutdefs.txt; if; ",
                                        exe_file.c_str(), tempdir_name, tempdir_name);
                else
                        buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos,
-                                       "%s -c 'read_verilog %s/input.v; read_library %s/stdcells.genlib; map; ",
+                                       "%s -s -c 'read_verilog %s/input.v; read_library %s/stdcells.genlib; map; ",
                                        exe_file.c_str(), tempdir_name, tempdir_name);
                if (lut_mode)
                        buffer_pos += snprintf(buffer+buffer_pos, 1024-buffer_pos, "write_blif %s/output.blif' 2>&1", tempdir_name);