[ARM] Fix, add tests for FP16 aapcs.

testsuite/
	* gcc.target/arm/aapcs/neon-vect10.c: Require
	-mfloat-ab=hard.  Replace arm_neon_fp16_ok with arm_neon_fp16_hw.
	* gcc.target/arm/aapcs/neon-vect9.c: Likewise.
	* gcc.target/arm/aapcs/vfp18.c: Likewise.
	* gcc.target/arm/aapcs/vfp19.c: Likewise.
	* gcc.target/arm/aapcs/vfp20.c: Likewise.
	* gcc.target/arm/aapcs/vfp21.c: Likewise.
	* gcc.target/arm/fp16-aapcs-1.c: Require
	-mfloat-ab=hard.  Also simplify the test.
	* gcc.target/arm/fp16-aapcs-2.c: New.

From-SVN: r237849

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index c51c1bcda58301112a994873db6878ff2844a446..c8f96a9873224e9e10b8d9662f87c94e3fdd40ce 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,16 @@
+2016-06-29  Matthew Wahab  <matthew.wahab@arm.com>
+
+       * gcc.target/arm/aapcs/neon-vect10.c: Require
+       -mfloat-ab=hard.  Replace arm_neon_fp16_ok with arm_neon_fp16_hw.
+       * gcc.target/arm/aapcs/neon-vect9.c: Likewise.
+       * gcc.target/arm/aapcs/vfp18.c: Likewise.
+       * gcc.target/arm/aapcs/vfp19.c: Likewise.
+       * gcc.target/arm/aapcs/vfp20.c: Likewise.
+       * gcc.target/arm/aapcs/vfp21.c: Likewise.
+       * gcc.target/arm/fp16-aapcs-1.c: Require
+       -mfloat-ab=hard.  Also simplify the test.
+       * gcc.target/arm/fp16-aapcs-2.c: New.
+
 2016-06-29  Matthew Wahab  <matthew.wahab@arm.com>
 
        * lib/target-supports.exp (add_options_for_arm_fp16): Reword

diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect10.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect10.c
index 680a3b560d709b309050a1e335aa0f51947903e1..788079bc104f927592199899407369940c28aae3 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect10.c
+++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect10.c
@@ -1,7 +1,8 @@
 /* Test AAPCS layout (VFP variant for Neon types) */
 
 /* { dg-do run { target arm_eabi } } */
-/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-require-effective-target arm_hard_vfp_ok }  */
+/* { dg-require-effective-target arm_neon_fp16_hw } */
 /* { dg-add-options arm_neon_fp16 } */
 
 #ifndef IN_FRAMEWORK

diff --git a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect9.c b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect9.c
index fc2b13bf1b77df308067a4a5f6e43d3d61405888..b42fdd23926c286a0edfa8897b97c0283a2de630 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/aapcs/neon-vect9.c
+++ b/gcc/testsuite/gcc.target/arm/aapcs/neon-vect9.c
@@ -1,7 +1,8 @@
 /* Test AAPCS layout (VFP variant for Neon types) */
 
 /* { dg-do run { target arm_eabi } } */
-/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-require-effective-target arm_hard_vfp_ok }  */
+/* { dg-require-effective-target arm_neon_fp16_hw } */
 /* { dg-add-options arm_neon_fp16 } */
 
 #ifndef IN_FRAMEWORK

diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp18.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp18.c
index 225e9ce7c108f0369b9b5ae2a6e24435c76c8a1a..0745a82f5e835147ddda46c8ae1e905294ff2714 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/aapcs/vfp18.c
+++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp18.c
@@ -1,8 +1,9 @@
-/* Test AAPCS layout (VFP variant) */
+/* Test AAPCS layout (VFP variant)  */
 
 /* { dg-do run { target arm_eabi } }  */
-/* { dg-require-effective-target arm_neon_fp16_ok } */
-/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard -mfp16-format=ieee" } */
+/* { dg-require-effective-target arm_hard_vfp_ok }  */
+/* { dg-require-effective-target arm_fp16_hw }  */
+/* { dg-add-options arm_fp16_ieee }  */
 
 #ifndef IN_FRAMEWORK
 #define VFP

diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp19.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp19.c
index 8928b1562e995804fae26d6c6ca9e78a8862627f..950c1f6a6d41dff0ebd91fc945dc2c3ff11503fb 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/aapcs/vfp19.c
+++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp19.c
@@ -1,8 +1,9 @@
-/* Test AAPCS layout (VFP variant) */
+/* Test AAPCS layout (VFP variant)  */
 
-/* { dg-do run { target arm_eabi } } */
-/* { dg-require-effective-target arm_neon_fp16_ok } */
-/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard -mfp16-format=ieee" } */
+/* { dg-do run { target arm_eabi } }  */
+/* { dg-require-effective-target arm_hard_vfp_ok }  */
+/* { dg-require-effective-target arm_fp16_hw }  */
+/* { dg-add-options arm_fp16_ieee }  */
 
 #ifndef IN_FRAMEWORK
 #define VFP

diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp20.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp20.c
index 61f07049f2cf59e28a4faee2dad5a07267cb5eb8..f898d4cebd700dbc18c7f8792b950a420639f47f 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/aapcs/vfp20.c
+++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp20.c
@@ -1,8 +1,9 @@
-/* Test AAPCS layout (VFP variant) */
+/* Test AAPCS layout (VFP variant)  */
 
-/* { dg-do run { target arm_eabi } } */
-/* { dg-require-effective-target arm_neon_fp16_ok } */
-/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard -mfp16-format=ieee" } */
+/* { dg-do run { target arm_eabi } }  */
+/* { dg-require-effective-target arm_hard_vfp_ok }  */
+/* { dg-require-effective-target arm_fp16_hw }  */
+/* { dg-add-options arm_fp16_ieee }  */
 
 #ifndef IN_FRAMEWORK
 #define VFP

diff --git a/gcc/testsuite/gcc.target/arm/aapcs/vfp21.c b/gcc/testsuite/gcc.target/arm/aapcs/vfp21.c
index 15dff7d19f8aa6e5268b301194c2142dddcebc2f..48bb59856e0ad6e48b842a7f35c4e599106704cd 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/aapcs/vfp21.c
+++ b/gcc/testsuite/gcc.target/arm/aapcs/vfp21.c
@@ -1,8 +1,9 @@
-/* Test AAPCS layout (VFP variant) */
+/* Test AAPCS layout (VFP variant)  */
 
-/* { dg-do run { target arm_eabi } } */
-/* { dg-require-effective-target arm_neon_fp16_ok } */
-/* { dg-options "-O -mfpu=vfp -mfloat-abi=hard -mfp16-format=ieee" } */
+/* { dg-do run { target arm_eabi } }  */
+/* { dg-require-effective-target arm_hard_vfp_ok }  */
+/* { dg-require-effective-target arm_fp16_hw }  */
+/* { dg-add-options arm_fp16_ieee }  */
 
 #ifndef IN_FRAMEWORK
 #define VFP

diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c b/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c
index 5eab3e2ca783c8a878a7b5d0c42a75a0e1572d5f..9bf3fc07e7fad008940987bb2a80e6ddd6a2650c 100644 (file)
--- a/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c
+++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-1.c
@@ -1,17 +1,21 @@
 /* { dg-do compile }  */
+/* { dg-require-effective-target arm_hard_vfp_ok }  */
 /* { dg-require-effective-target arm_fp16_ok } */
-/* { dg-options "-mfp16-format=ieee -O2" }  */
-/* { dg-add-options arm_fp16 } */
+/* { dg-options "-O2" }  */
+/* { dg-add-options arm_fp16_ieee } */
 
-/* Test __fp16 arguments and return value in registers.  */
+/* Test __fp16 arguments and return value in registers (hard-float).  */
 
-__fp16 F (__fp16 a, __fp16 b, __fp16 c)
+void
+swap (__fp16, __fp16);
+
+__fp16
+F (__fp16 a, __fp16 b, __fp16 c)
 {
-  if (a == b)
-    return c;
-  return a;
+  swap (b, a);
+  return c;
 }
 
-/* { dg-final { scan-assembler-times {vcvtb\.f32\.f16\ts[0-9]+, s0} 1 } }  */
-/* { dg-final { scan-assembler-times {vcvtb\.f32\.f16\ts[0-9]+, s1} 1 } }  */
-/* { dg-final { scan-assembler-times {vmov\ts0, r[0-9]+} 1 } }  */
+/* { dg-final { scan-assembler-times {vmov\tr[0-9]+, s[0-2]} 2 } }  */
+/* { dg-final { scan-assembler-times {vmov.f32\ts1, s0} 1 } }  */
+/* { dg-final { scan-assembler-times {vmov\ts0, r[0-9]+} 2 } }  */

diff --git a/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c b/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c
new file mode 100644 (file)
index 0000000..4753e36
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/fp16-aapcs-2.c
@@ -0,0 +1,21 @@
+/* { dg-do compile }  */
+/* { dg-require-effective-target arm_fp16_ok } */
+/* { dg-options "-mfloat-abi=softfp -O2" }  */
+/* { dg-add-options arm_fp16_ieee } */
+/* { dg-skip-if "incompatible float-abi" { arm*-*-* } { "-mfloat-abi=hard" } } */
+
+/* Test __fp16 arguments and return value in registers (softfp).  */
+
+void
+swap (__fp16, __fp16);
+
+__fp16
+F (__fp16 a, __fp16 b, __fp16 c)
+{
+  swap (b, a);
+  return c;
+}
+
+/* { dg-final { scan-assembler-times {mov\tr[0-9]+, r[0-2]} 3 } }  */
+/* { dg-final { scan-assembler-times {mov\tr1, r0} 1 } }  */
+/* { dg-final { scan-assembler-times {mov\tr0, r[0-9]+} 2 } }  */