---------- Begin Simulation Statistics ----------
sim_seconds 0.000729 # Number of seconds simulated
-sim_ticks 728599000 # Number of ticks simulated
-final_tick 728599000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 729071000 # Number of ticks simulated
+final_tick 729071000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1327611 # Simulator instruction rate (inst/s)
-host_op_rate 1327594 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 483660925 # Simulator tick rate (ticks/s)
-host_mem_usage 267288 # Number of bytes of host memory used
-host_seconds 1.51 # Real time elapsed on the host
-sim_insts 1999897 # Number of instructions simulated
-sim_ops 1999897 # Number of ops (including micro ops) simulated
+host_inst_rate 1157540 # Simulator instruction rate (inst/s)
+host_op_rate 1157526 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 421963637 # Simulator tick rate (ticks/s)
+host_mem_usage 274580 # Number of bytes of host memory used
+host_seconds 1.73 # Real time elapsed on the host
+sim_insts 1999959 # Number of instructions simulated
+sim_ops 1999959 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::cpu0.inst 25792 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 29056 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 25792 # Number of bytes read from this memory
system.physmem.num_reads::cpu3.inst 403 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 454 # Number of read requests responded to by this memory
system.physmem.num_reads::total 3428 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 35399445 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 39879275 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 35399445 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 39879275 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 35399445 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 39879275 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 35399445 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 39879275 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 301114879 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 35399445 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 35399445 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 35399445 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 35399445 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 141597779 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 35399445 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 39879275 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 35399445 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 39879275 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 35399445 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 39879275 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 35399445 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 39879275 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 301114879 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 35376527 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 39853457 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 35376527 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 39853457 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 35376527 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 39853457 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 35376527 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 39853457 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 300919938 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 35376527 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 35376527 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 35376527 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 35376527 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 141506108 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 35376527 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 39853457 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 35376527 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 39853457 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 35376527 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 39853457 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 35376527 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 39853457 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 300919938 # Total bandwidth to/from this memory (bytes/s)
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
system.cpu0.workload.num_syscalls 18 # Number of system calls
-system.cpu0.numCycles 1457198 # number of cpu cycles simulated
+system.cpu0.numCycles 1458142 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 500001 # Number of instructions committed
system.cpu0.num_load_insts 124443 # Number of load instructions
system.cpu0.num_store_insts 56350 # Number of store instructions
system.cpu0.num_idle_cycles 0 # Number of idle cycles
-system.cpu0.num_busy_cycles 1457198 # Number of busy cycles
+system.cpu0.num_busy_cycles 1458142 # Number of busy cycles
system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0 # Percentage of idle cycles
system.cpu0.icache.replacements 152 # number of replacements
-system.cpu0.icache.tagsinuse 216.402080 # Cycle average of tags in use
+system.cpu0.icache.tagsinuse 216.378486 # Cycle average of tags in use
system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks.
system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 216.402080 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.422660 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.422660 # Average percentage of cache occupancy
+system.cpu0.icache.occ_blocks::cpu0.inst 216.378486 # Average occupied blocks per requestor
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+system.cpu0.icache.occ_percent::total 0.422614 # Average percentage of cache occupancy
system.cpu0.icache.ReadReq_hits::cpu0.inst 499557 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 499557 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 499557 # number of demand (read+write) hits
system.cpu0.icache.demand_misses::total 463 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 463 # number of overall misses
system.cpu0.icache.overall_misses::total 463 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 23115500 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 23115500 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 23115500 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 23115500 # number of demand (read+write) miss cycles
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system.cpu0.icache.ReadReq_accesses::cpu0.inst 500020 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 500020 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 500020 # number of demand (read+write) accesses
system.cpu0.icache.demand_miss_rate::total 0.000926 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000926 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.000926 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 49925.485961 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 49925.485961 # average ReadReq miss latency
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-system.cpu0.icache.demand_avg_miss_latency::total 49925.485961 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 49925.485961 # average overall miss latency
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+system.cpu0.icache.overall_avg_miss_latency::total 49982.721382 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.demand_mshr_misses::total 463 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 463 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 463 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 22189500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 22189500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 22189500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 22189500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 22189500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 22189500 # number of overall MSHR miss cycles
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+system.cpu0.icache.overall_mshr_miss_latency::total 22216000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.000926 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.000926 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000926 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.000926 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47925.485961 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47925.485961 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47925.485961 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 47925.485961 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47925.485961 # average overall mshr miss latency
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 61 # number of replacements
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system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::cpu0.data 273.541050 # Average occupied blocks per requestor
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-system.cpu0.dcache.occ_percent::total 0.534260 # Average percentage of cache occupancy
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system.cpu0.dcache.ReadReq_hits::cpu0.data 124111 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 124111 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 56201 # number of WriteReq hits
system.cpu0.dcache.demand_misses::total 463 # number of demand (read+write) misses
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system.cpu0.dcache.overall_misses::total 463 # number of overall misses
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system.cpu0.dcache.ReadReq_accesses::cpu0.data 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 124435 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 56340 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.demand_miss_rate::total 0.002561 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.002561 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.002561 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 53929.012346 # average ReadReq miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002604 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002604 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002467 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.002561 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002561 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.002561 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 51929.012346 # average ReadReq mshr miss latency
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system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002604 # mshr miss rate for ReadReq accesses
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system.cpu3.dtb.fetch_misses 0 # ITB misses
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system.cpu3.itb.data_acv 0 # DTB access violations
system.cpu3.itb.data_accesses 0 # DTB accesses
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system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu3.num_fp_register_reads 32 # number of times the floating registers were read
system.cpu3.num_fp_register_writes 16 # number of times the floating registers were written
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system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles
system.cpu3.idle_fraction 0 # Percentage of idle cycles
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff