// This shregmap call infers fixed length shift registers after abc
// has performed any necessary retiming
if (!nosrl || help_mode)
- run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
- std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/ff_map.v";
- if (abc9)
+ run("xilinx_srl -fixed -minlen 3", "(skip if '-nosrl')");
-
+ std::string techmap_args = "-map +/xilinx/lut_map.v -map +/xilinx/cells_map.v";
+ if (help_mode)
- techmap_args += " [-map +/xilinx/ff_map.v]";
- else if (!abc9)
- techmap_args += " -map +/xilinx/ff_map.v";
++ techmap_args += " [-map +/xilinx/ff_map.v]";
++ else if (abc9)
+ techmap_args += " -map +/xilinx/abc_unmap.v";
++ else
++ techmap_args += " -map +/xilinx/ff_map.v";
run("techmap " + techmap_args);
- run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
- "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
- if (!abc9)
++ if (!abc9 || help_mode)
+ run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+ "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT", "(without '-abc9' only)");
run("clean");
}