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diff --git a/openpower/sv/sprs.mdwn b/openpower/sv/sprs.mdwn
index c81c59a2739b0586ff529c36526683fc7ffd872b..74d4b0e12c0966e24de44807f10f22c991a75106 100644 (file)
--- a/openpower/sv/sprs.mdwn
+++ b/openpower/sv/sprs.mdwn
@@ -95,12 +95,18 @@ mfspr) are 100% guaranteed to have zero impact on SVP64 state.
 
 **Max Vector Length (maxvl)** <a name="mvl" />
 
-MAXVECTORLENGTH is the same concept as MVL in RISC-V RVV, except that it
-is variable length and may be dynamically set (normally from an immediate
-field only).  MVL is limited to 7 bits
+MAXVECTORLENGTH is a static (immediate-operand only) compile-time declaration
+of the maximum number of elements in a Vector. MVL is limited to 7 bits
 (in the first version of SVP64) and consequently the maximum number of
 elements is limited to between 0 and 127.
 
+MAXVL is normally (in other True-Scalable Vector ISAs) an Architecturally-defined
+quantity related indirectly to the total available number of bits in the Vector
+Register File.  Cray Vectors had a Hardware-Architectural set limit of MAXVL=64.
+RISC-V RVV has MAXVL defined in terms of a Silicon-Partner-selectable fixed number
+of bits.  MAXVL in Simple-V is set in terms of the number of *elements* and
+may change at runtime.
+
 Programmer's Note: Except by directly using `mtspr` on SVSTATE, which may
 result in performance penalties on some hardware implementations, SVSTATE's `maxvl`
 field may only be set **statically** as an immediate, by the `setvl` instruction.
@@ -119,9 +125,11 @@ instruction for setting Vector Length.
 equivalent. Similar to RVV, VL is set to be within
 the range 0 <= VL <= MVL. Unlike RVV, VL is set **exactly** according to the following:
 
+```
     VL = (RT|0) = MIN(vlen, MVL)
+```
 
-where 0 <= MVL <= 127 and vlen may come from an immediate, `RA`, or from the `CTR` SPR,
+where `0 <= MVL <= 127`, and vlen may come from an immediate, `RA`, or from the `CTR` SPR,
 depending on options selected with the `setvl` instruction.
 
 Programmer's Note: conceptual understanding of Cray-style Vectors is far beyond the scope
@@ -129,26 +137,6 @@ of the Power ISA Technical Reference.  Guidance on the 50-year-old Cray Vector p
 best sought elsewhere: good studies include Academic Courses given on the 1970s
 Cray Supercomputers over at least the past three decades.
 
-**SUBVL - Sub Vector Length**
-
-This is a "group by quantity" that effectively asks each iteration
-of the hardware loop to load SUBVL elements of width elwidth at a
-time. Effectively, SUBVL is like a SIMD multiplier: instead of just 1
-operation issued, SUBVL operations are issued.
-
-The main effect of SUBVL is that predication bits are applied per
-**group**, rather than by individual element.  Legal values are 0 to 3,
-representing 1 operation (1 element) thru 4 operations (4 elements) respectively.
-Elements are best though of in the context of 3D, Audio and Video: two Left and Right
-Channel "elements" or four ARGB "elements", or three XYZ coordinate "elements".
-
-`subvl` is again primarily set by the `setvl` instruction. Not to be confused
-with `hphint`.
-
-Directly related to `subvl` is the `pack` and `unpack` Mode bits of `SVSTATE`.
-See `svstep` instruction for how to set Pack and Unpack Modes.
-
-
 **Horizontal Parallelism**
 
 A problem exists for hardware where it may not be able to detect