Added missing ports and parameters to xilinx brams

diff --git a/techlibs/xilinx/brams_map.v b/techlibs/xilinx/brams_map.v
index af057fe1f58121f3725c26a7fb022169cba830a6..2e9bba9a999f9364b2f7da49291422ceb697793a 100644 (file)
--- a/techlibs/xilinx/brams_map.v
+++ b/techlibs/xilinx/brams_map.v
@@ -31,7 +31,8 @@ module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
                .WRITE_MODE_A("READ_FIRST"),
                .WRITE_MODE_B("READ_FIRST"),
                .IS_CLKARDCLK_INVERTED(!CLKPOL2),
-               .IS_CLKBWRCLK_INVERTED(!CLKPOL3)
+               .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
+               .SIM_DEVICE("7SERIES")
        ) _TECHMAP_REPLACE_ (
                .DOBDO(DO[63:32]),
                .DOADO(DO[31:0]),
@@ -92,7 +93,8 @@ module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
                .WRITE_MODE_A("READ_FIRST"),
                .WRITE_MODE_B("READ_FIRST"),
                .IS_CLKARDCLK_INVERTED(!CLKPOL2),
-               .IS_CLKBWRCLK_INVERTED(!CLKPOL3)
+               .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
+               .SIM_DEVICE("7SERIES")
        ) _TECHMAP_REPLACE_ (
                .DOBDO(DO[31:16]),
                .DOADO(DO[15:0]),
@@ -148,6 +150,9 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
        wire [3:0] DIP, DOP;
        wire [31:0] DI, DO;
 
+       wire [31:0] DOBDO;
+       wire [3:0] DOPBDOP;
+
        assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
        assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
 
@@ -160,7 +165,8 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
                .WRITE_MODE_A("READ_FIRST"),
                .WRITE_MODE_B("READ_FIRST"),
                .IS_CLKARDCLK_INVERTED(!CLKPOL2),
-               .IS_CLKBWRCLK_INVERTED(!CLKPOL3)
+               .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
+               .SIM_DEVICE("7SERIES")
        ) _TECHMAP_REPLACE_ (
                .DIADI(32'd0),
                .DIPADIP(4'd0),
@@ -176,6 +182,8 @@ module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 
                .DIBDI(DI),
                .DIPBDIP(DIP),
+               .DOBDO(DOBDO),
+               .DOPBDOP(DOPBDOP),
                .ADDRBWRADDR(B1ADDR_16),
                .CLKBWRCLK(CLK3),
                .ENBWREN(|1),
@@ -213,6 +221,9 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
        wire [1:0] DIP, DOP;
        wire [15:0] DI, DO;
 
+       wire [15:0] DOBDO;
+       wire [1:0] DOPBDOP;
+
        assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] };
        assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA;
 
@@ -225,7 +236,8 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
                .WRITE_MODE_A("READ_FIRST"),
                .WRITE_MODE_B("READ_FIRST"),
                .IS_CLKARDCLK_INVERTED(!CLKPOL2),
-               .IS_CLKBWRCLK_INVERTED(!CLKPOL3)
+               .IS_CLKBWRCLK_INVERTED(!CLKPOL3),
+               .SIM_DEVICE("7SERIES")
        ) _TECHMAP_REPLACE_ (
                .DIADI(16'b0),
                .DIPADIP(2'b0),
@@ -241,6 +253,8 @@ module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
 
                .DIBDI(DI),
                .DIPBDIP(DIP),
+               .DOBDO(DOBDO),
+               .DOPBDOP(DOPBDOP),
                .ADDRBWRADDR(B1ADDR_14),
                .CLKBWRCLK(CLK3),
                .ENBWREN(|1),