soc/cores/clock: allow ClockSignal to be used for clkin

diff --git a/litex/soc/cores/clock.py b/litex/soc/cores/clock.py
index a007bf74df1d2e6409040f4b1f7e4fcfcc82ba0a..44858447c3625b310d22c6aa4874c0785f169686 100644 (file)
--- a/litex/soc/cores/clock.py
+++ b/litex/soc/cores/clock.py
@@ -33,7 +33,7 @@ class S7Clocking(Module, AutoCSR):
 
     def register_clkin(self, clkin, freq):
         self.clkin = Signal()
-        if isinstance(clkin, Signal):
+        if isinstance(clkin, (Signal, ClockSignal)):
             self.comb += self.clkin.eq(clkin)
         elif isinstance(clkin, Record):
             self.specials += DifferentialInput(clkin.p, clkin.n, self.clkin)
@@ -224,7 +224,7 @@ class USClocking(Module, AutoCSR):
 
     def register_clkin(self, clkin, freq):
         self.clkin = Signal()
-        if isinstance(clkin, Signal):
+        if isinstance(clkin, (Signal, ClockSignal)):
             self.comb += self.clkin.eq(clkin)
         elif isinstance(clkin, Record):
             self.specials += DifferentialInput(clkin.p, clkin.n, self.clkin)
@@ -413,7 +413,7 @@ class ECP5PLL(Module):
         assert freq >= clki_freq_min
         assert freq <= clki_freq_max
         self.clkin = Signal()
-        if isinstance(clkin, Signal):
+        if isinstance(clkin, (Signal, ClockSignal)):
             self.comb += self.clkin.eq(clkin)
         else:
             raise ValueError