(no commit message)

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index 13285b6cd68f93d54f9f2508485ebe73c0cab7e2..b2731eb3eb4ccbe42ea40af9591c0f40af8e3e66 100644 (file)
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -1744,6 +1744,49 @@ about future LD/STs.  Therefore, Fail-First LD/ST in Vertical-First is
 `UNDEFINED`.  This is very different from Arithmetic (Data-dependent)
 FFirst where Vertical-First Mode is fully deterministic, not speculative.
 
+## Data-Dependent Fail-First (not Fail/Fault-First)
+
+Not to be confused with Fail/Fault First, Data-Fail-First performs an
+additional check on the data into a Condition Register Field and if a test on
+the CR Field fails then VL is truncated and further looping terminates.
+This is precisely the same as Arithmetic Data-Dependent Fail-First, the
+only difference being that the result comes from the LD/ST.
+
+In the case of Store operations there is a quirk when VLi (VL inclusive
+is "Valid") is clear. Bear in mind the riteria is that the truncated
+Vector of results,
+when VLi is clear, must all pass the "test", but when VLi is set the
+*current failed test* is permitted to be included.  Thus, the actual
+update (store) to Memory is **not permitted to take place** should the
+test fail. Therefore, on testing the value to be stored, and after updating
+the corresponding CR Field Element, when VLi=0 and finding that the
+test fails the Memory store must **not** occur.  By contrast if VLi=1
+and the test the Store may proceed *and then* looping terminates.
+In this way, when non-Inclusive, the Vector of Truncated results contains
+only Stores that passed the test, and when Inclusive the Vector of
+Truncated results contains the first-failed data.
+
+Below is an example of loading the starting addresses of Linked-List nodes.
+If VLi=1 it will load the NULL pointer into the Vector of results.
+If however VLi=0 it will *exclude* the NULL pointer by truncating VL to
+one Element earlier.
+
+```
+   RT=1 # vec - deliberately overlaps by one with RA
+   RA=0 # vec - first one is valid, contains ptr
+   imm = 8 # offset_of(ptr->next)
+   for i in range(VL):
+       EA = GPR(RA+i) + imm          # ptr + offset(next)
+       data = MEM(EA, 8)             # 64-bit address of ptr->next
+       GPR(RT+i) = data              # happens to be read on next loop!
+       # was a normal ld up to this point. now the Data-Fail-First
+       CR.field(i) = conditions(data)
+       if CR.field(i).EQ == testbit: # check if zero
+           if VLI then   VL = i+1                   # update VL, inclusive
+           else          VL = i                     # update VL
+           break                     # stop looping
+```
+
 ## LOAD/STORE Elwidths <a name="elwidth"></a>
 
 Loads and Stores are almost unique in that the Power Scalar ISA