projects
/
yosys.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
0ca397f
)
Do not sigmap!
author
Eddie Hung
<eddie@fpgeh.com>
Tue, 20 Aug 2019 22:23:26 +0000
(15:23 -0700)
committer
Eddie Hung
<eddie@fpgeh.com>
Tue, 20 Aug 2019 22:23:26 +0000
(15:23 -0700)
backends/aiger/xaiger.cc
patch
|
blob
|
history
diff --git
a/backends/aiger/xaiger.cc
b/backends/aiger/xaiger.cc
index ad2a778fa6d00da6375d5a3844e92e3827d7d9c9..d02997da44bc609cf3b08726076751d7280f1cc9 100644
(file)
--- a/
backends/aiger/xaiger.cc
+++ b/
backends/aiger/xaiger.cc
@@
-355,7
+355,7
@@
struct XAigerWriter
log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
if (is_input) {
- for (auto b :
sigmap(c.second)
) {
+ for (auto b :
c.second
) {
Wire *w = b.wire;
if (!w) continue;
if (!w->port_output || !cell_known) {
@@
-381,7
+381,7
@@
struct XAigerWriter
}
}
- for (auto b :
sigmap(c.second)
) {
+ for (auto b :
c.second
) {
Wire *w = b.wire;
if (!w) continue;
input_bits.insert(b);