Connect dramcore to SoC bus in ECPIX-5 example

diff --git a/examples/ecpix5.py b/examples/ecpix5.py
index d4251bcef2f124a426dc5787d3ad17cdcc5b12de..3848436de26ef3e2a77c2d6439e348ed75199480 100644 (file)
--- a/examples/ecpix5.py
+++ b/examples/ecpix5.py
@@ -152,7 +152,9 @@ class DDR3SoC(CPUSoC, Elaboratable):
                        geom_settings   = ddrmodule.geom_settings,
                        timing_settings = ddrmodule.timing_settings,
                        clk_freq = clk_freq)
-               #self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
+               self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
+
+               self.dramport = self.dramcore.crossbar.get_port()
 
                self.memory_map = self._decoder.bus.memory_map