A_SIGNED == B_SIGNED so flip both

diff --git a/techlibs/common/mul2dsp.v b/techlibs/common/mul2dsp.v
index 258ddf021344914159c63c120e8b0e0dc88cc01c..d195996202c6df5cdfa78925e631c696acbf8343 100644 (file)
--- a/techlibs/common/mul2dsp.v
+++ b/techlibs/common/mul2dsp.v
@@ -34,31 +34,22 @@ module \$mul (A, B, Y);
        output [Y_WIDTH-1:0] Y;\r
 \r
        generate\r
-        if (`DSP_A_SIGNEDONLY && !A_SIGNED) begin\r
-            wire dummy;\r
+        localparam add_sign_A = `DSP_A_SIGNEDONLY && !A_SIGNED;\r
+        localparam add_sign_B = `DSP_B_SIGNEDONLY && !B_SIGNED;\r
+        if (add_sign_A || add_sign_B) begin\r
+            if (add_sign_A && add_sign_B)\r
+                wire [1:0] dummy;\r
+            else\r
+                wire dummy;\r
                        \$mul #(\r
                                .A_SIGNED(1),\r
-                               .B_SIGNED(B_SIGNED),\r
-                               .A_WIDTH(A_WIDTH+1),\r
-                               .B_WIDTH(B_WIDTH),\r
-                               .Y_WIDTH(Y_WIDTH+1)\r
-                       ) _TECHMAP_REPLACE_ (\r
-                               .A({1'b0, A}),\r
-                               .B(B),\r
-                               .Y({dummy, Y})\r
-                       );\r
-        end\r
-        else if (`DSP_B_SIGNEDONLY && !B_SIGNED) begin\r
-            wire dummy;\r
-                       \$mul #(\r
-                               .A_SIGNED(A_SIGNED),\r
                                .B_SIGNED(1),\r
-                               .A_WIDTH(A_WIDTH),\r
-                               .B_WIDTH(B_WIDTH+1),\r
-                               .Y_WIDTH(Y_WIDTH+1)\r
+                               .A_WIDTH(A_WIDTH + (add_sign_A ? 1 : 0)),\r
+                               .B_WIDTH(B_WIDTH + (add_sign_B ? 1 : 0)),\r
+                               .Y_WIDTH(Y_WIDTH + (add_sign_A ? 1 : 0) + (add_sign_B ? 1 : 0))\r
                        ) _TECHMAP_REPLACE_ (\r
-                               .A(A),\r
-                               .B({1'b0, B}),\r
+                               .A(add_sign_A ? {1'b0, A} : A),\r
+                               .B(add_sign_B ? {1'b0, B} : B),\r
                                .Y({dummy, Y})\r
                        );\r
         end\r