[AArch64] Fix PR87511

As mentioned in PR87511, the shift used in aarch64_mask_and_shift_for_ubfiz_p
should be evaluated as a HOST_WIDE_INT rather than int.

Passes bootstrap & regress.

    gcc/
	PR target/87511
	* config/aarch64/aarch64.c (aarch64_mask_and_shift_for_ubfiz_p):
	Use HOST_WIDE_INT_1U for shift.

    testsuite/
	PR target/87511
	* gcc.target/aarch64/pr87511.c: Add new test.

From-SVN: r265058

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 8172fcd927646f4db3f5503c6712cd0ce907d03a..b908601ce03f921e0691734e16f88de47377881d 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2018-10-11  Wilco Dijkstra  <wdijkstr@arm.com>
+
+       PR target/87511
+       * config/aarch64/aarch64.c (aarch64_mask_and_shift_for_ubfiz_p):
+       Use HOST_WIDE_INT_1U for shift.
+
 2018-10-11  Doug Rupp  <rupp@adacore.com>
             Olivier Hainque  <hainque@adacore.com>
 

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index d385b246a74517f09446600a3bf48c52ef2de5f1..4c7790826658539f71f2fd9eb9ea0329081938be 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -8842,7 +8842,8 @@ aarch64_mask_and_shift_for_ubfiz_p (scalar_int_mode mode, rtx mask,
   return CONST_INT_P (mask) && CONST_INT_P (shft_amnt)
         && INTVAL (shft_amnt) < GET_MODE_BITSIZE (mode)
         && exact_log2 ((INTVAL (mask) >> INTVAL (shft_amnt)) + 1) >= 0
-        && (INTVAL (mask) & ((1 << INTVAL (shft_amnt)) - 1)) == 0;
+        && (INTVAL (mask)
+            & ((HOST_WIDE_INT_1U << INTVAL (shft_amnt)) - 1)) == 0;
 }
 
 /* Calculate the cost of calculating X, storing it in *COST.  Result

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index a1ba7da09b832142f94da158e3d2bd9dbc0d44eb..f026cb260648a6b5329f6087bcc557a9f60bd3cc 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-10-11  Wilco Dijkstra  <wdijkstr@arm.com>
+
+       PR target/87511
+       * gcc.target/aarch64/pr87511.c: Add new test.
+
 2018-10-11  David Malcolm  <dmalcolm@redhat.com>
 
        PR c++/84993

diff --git a/gcc/testsuite/gcc.target/aarch64/pr87511.c b/gcc/testsuite/gcc.target/aarch64/pr87511.c
new file mode 100644 (file)
index 0000000..9806470
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/pr87511.c
@@ -0,0 +1,16 @@
+/* { dg-do assemble } */
+/* { dg-options "-Os" } */
+
+int a, d;
+struct {
+  signed f5 : 26;
+  signed f6 : 12;
+} b;
+signed char c;
+void fn1() {
+  signed char *e = &c;
+  d = a * 10;
+  *e = d;
+  b.f6 = c;
+  b.f5 = 8 <= 3;
+}