Import utils using the absolute module path

diff --git a/gram/test/test_common.py b/gram/test/test_common.py
index 385282c613c50d5d4be385746677b685c4aee1a6..720547809d9cbb7064708791925bf1d5f1c11c1c 100644 (file)
--- a/gram/test/test_common.py
+++ b/gram/test/test_common.py
@@ -3,7 +3,7 @@ from nmigen import *
 from nmigen.hdl.ast import Past
 
 from gram.common import tXXDController, tFAWController
-from utils import *
+from gram.test.utils import *
 
 class tXXDControllerTestCase(FHDLTestCase):
     def test_formal(self):

diff --git a/gram/test/test_compat.py b/gram/test/test_compat.py
index 679a32812d03ce7ab4587cbf5655a3256ef7be20..47934729662ba1454d553667b2a7f34070678c61 100644 (file)
--- a/gram/test/test_compat.py
+++ b/gram/test/test_compat.py
@@ -4,7 +4,7 @@ from nmigen.hdl.ast import Past
 from nmigen.asserts import Assert, Assume
 
 from gram.compat import *
-from utils import *
+from gram.test.utils import *
 
 class DelayedEnterTestCase(FHDLTestCase):
     def test_sequence(self):

diff --git a/gram/test/test_core_crossbar.py b/gram/test/test_core_crossbar.py
index a2da8aab593155c7272a0a9a4ebf021a31a24fc8..7d89f0b7b424911aeeeff9ad704c28830b09210b 100644 (file)
--- a/gram/test/test_core_crossbar.py
+++ b/gram/test/test_core_crossbar.py
@@ -3,7 +3,7 @@ from nmigen.hdl.ast import Sample
 from nmigen.asserts import Assert, Assume
 
 from gram.core.crossbar import _DelayLine
-from utils import *
+from gram.test.utils import *
 
 class DelayLineSpec(Elaboratable):
     def __init__(self, delay):

diff --git a/gram/test/test_core_multiplexer.py b/gram/test/test_core_multiplexer.py
index 4d5c85865025daf14fe57421cc1b73465a63e779..0643b02067c5a9652bffb82b433c2c7af882d972 100644 (file)
--- a/gram/test/test_core_multiplexer.py
+++ b/gram/test/test_core_multiplexer.py
@@ -3,7 +3,7 @@ from nmigen import *
 from gram.core.multiplexer import _AntiStarvation, _CommandChooser
 from gram.common import cmd_request_rw_layout
 import gram.stream as stream
-from utils import *
+from gram.test.utils import *
 
 class CommandChooserTestCase(FHDLTestCase):
     def prepare_testbench(self):

diff --git a/gram/test/test_core_refresher.py b/gram/test/test_core_refresher.py
index a9685364d2351ac70d5cfa51b6c3dfde987375ff..7460442edcfb705ed91b0352d3788772b56f1b08 100644 (file)
--- a/gram/test/test_core_refresher.py
+++ b/gram/test/test_core_refresher.py
@@ -4,7 +4,7 @@ from nmigen.asserts import Assert, Assume
 
 from gram.core.refresher import RefreshExecuter, RefreshSequencer, RefreshTimer, RefreshPostponer, Refresher
 from gram.compat import *
-from utils import *
+from gram.test.utils import *
 
 class RefreshExecuterTestCase(FHDLTestCase):
     def test_executer(self):

diff --git a/gram/test/test_dfii.py b/gram/test/test_dfii.py
index 195c9171916a24e86fa07824008d07fc785eaf4c..7016da185e0566e63c7c3c180a27149420fe3561 100644 (file)
--- a/gram/test/test_dfii.py
+++ b/gram/test/test_dfii.py
@@ -3,7 +3,7 @@ from lambdasoc.periph import Peripheral
 
 from gram.dfii import *
 from gram.phy.dfi import Interface
-from utils import *
+from gram.test.utils import *
 
 # Phase injector CSR addresses
 PI_COMMAND_ADDR = 0x00

diff --git a/gram/test/test_soc.py b/gram/test/test_soc.py
index fae835cf5ebfedbf4ac54dff15c41fb28fe9809f..d086b91a8fa5aed6bb723700b7aae3a266446094 100644 (file)
--- a/gram/test/test_soc.py
+++ b/gram/test/test_soc.py
@@ -17,7 +17,7 @@ from gram.modules import MT41K256M16
 from gram.frontend.wishbone import gramWishbone
 
 from gram.core.multiplexer import _AntiStarvation
-from utils import *
+from gram.test.utils import *
 
 class DDR3SoC(SoC, Elaboratable):
     def __init__(self, *, clk_freq, dramcore_addr,