radv: fix using LOAD_CONTEXT_REG with old GFX ME firmwares on GFX8

This fixes a critical issue.

Cc: <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109575
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 989372e48b782ac532d4d949e8c1fb8d8eb79a05..ad0b934ddfc6cbb00883f7c9779b03e63884fee1 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1373,7 +1373,7 @@ radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
 
        uint32_t reg = R_028028_DB_STENCIL_CLEAR + 4 * reg_offset;
 
-       if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
+       if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
                radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, 0));
                radeon_emit(cs, va);
                radeon_emit(cs, va >> 32);
@@ -1535,14 +1535,13 @@ radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,
 
        uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
 
-       if (cmd_buffer->device->physical_device->rad_info.chip_class >= VI) {
+       if (cmd_buffer->device->physical_device->has_load_ctx_reg_pkt) {
                radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG, 3, cmd_buffer->state.predicating));
                radeon_emit(cs, va);
                radeon_emit(cs, va >> 32);
                radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
                radeon_emit(cs, 2);
        } else {
-               /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
                radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
                radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) |
                                COPY_DATA_DST_SEL(COPY_DATA_REG) |

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 0fef92773e19e302e5e756019a6ca7883b0333b1..9509b3db13c9209c37a42df5c412686d7927fd80 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -369,6 +369,11 @@ radv_physical_device_init(struct radv_physical_device *device,
        device->dcc_msaa_allowed =
                (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
 
+       /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
+       device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
+                                      (device->rad_info.chip_class >= VI &&
+                                       device->rad_info.me_fw_feature >= 41);
+
        radv_physical_device_init_mem_types(device);
        radv_fill_device_extension_table(device, &device->supported_extensions);
 

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 1e38a12a2a77603aa098028a67074f7b1c7de393..9ce0724cb9f57c4e87d4800e59ad34aa077be88c 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -306,6 +306,9 @@ struct radv_physical_device {
        /* Whether DCC should be enabled for MSAA textures. */
        bool dcc_msaa_allowed;
 
+       /* Whether LOAD_CONTEXT_REG packets are supported. */
+       bool has_load_ctx_reg_pkt;
+
        /* This is the drivers on-disk cache used as a fallback as opposed to
         * the pipeline cache defined by apps.
         */