bus/dfi: fix multiphase naming

diff --git a/migen/bus/dfi.py b/migen/bus/dfi.py
index b2137cb399513ec259fac64f6d636d6d6f8d9f5d..b6f407d5c82d1dd2fe316f8ae6b9f7c986e3449a 100644 (file)
--- a/migen/bus/dfi.py
+++ b/migen/bus/dfi.py
@@ -34,9 +34,9 @@ class Interface:
                                if (m2s and signal[0] == M_TO_S) or (s2m and signal[0] == S_TO_M):
                                        if add_suffix:
                                                if signal[0] == M_TO_S:
-                                                       suffix = "_p" + int(n)
+                                                       suffix = "_p" + str(n)
                                                else:
-                                                       suffix = "_w" + int(n)
+                                                       suffix = "_w" + str(n)
                                        else:
                                                suffix = ""
                                        r.append(("dfi_" + signal[1] + suffix, getattr(phase, signal[1])))