No need to punch ports at all

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 65792421f570fb7e3e8a344f7f466908de9a7cf9..4bdd54772dd8d0fbf157a1debd1299eabab0e94d 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -481,6 +481,7 @@ struct XAigerWriter
                                        }
                                }
 
+                               // Connect $currQ as an input to the flop box
                                if (box_module->get_bool_attribute("\\abc9_flop")) {
                                        IdString port_name = "\\$currQ";
                                        Wire *w = box_module->wire(port_name);
@@ -786,6 +787,29 @@ struct XAigerWriter
                                        }
                                }
 
+                               // For flops only, create an extra input for $currQ
+                               if (box_module->get_bool_attribute("\\abc9_flop")) {
+                                       log_assert(holes_cell);
+
+                                       Wire *w = box_module->wire("\\$currQ");
+                                       Wire *holes_wire;
+                                       RTLIL::SigSpec port_wire;
+                                       for (int i = 0; i < GetSize(w); i++) {
+                                               box_inputs++;
+                                               holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
+                                               if (!holes_wire) {
+                                                       holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
+                                                       holes_wire->port_input = true;
+                                                       holes_wire->port_id = port_id++;
+                                                       holes_module->ports.push_back(holes_wire->name);
+                                               }
+                                               port_wire.append(holes_wire);
+                                       }
+                                       w = holes_module->addWire(stringf("%s.$currQ", cell->name.c_str()), GetSize(w));
+                                       w->set_bool_attribute("\\hierconn");
+                                       holes_module->connect(w, port_wire);
+                               }
+
                                write_h_buffer(box_inputs);
                                write_h_buffer(box_outputs);
                                write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int());

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index ce057566c5151f531f18c6c6e8f0922f973e3ded..777ec6ac8fecf8198c4a036df0d7976a2e67ea2b 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -1121,19 +1121,6 @@ struct Abc9Pass : public Pass {
                                        Pass::call_on_module(design, derived_module, "proc");
                                SigMap derived_sigmap(derived_module);
 
-                               Wire *currQ = derived_module->wire("\\$currQ");
-                               if (currQ == NULL)
-                                       log_error("'\\$currQ' is not a wire present in module '%s'.\n", log_id(cell->type));
-                               log_assert(!currQ->port_output);
-                               if (!currQ->port_input) {
-                                       currQ->port_input = true;
-                                       derived_module->ports.push_back(currQ->name);
-                                       currQ->port_id = GetSize(derived_module->ports);
-#ifndef NDEBUG
-                                       derived_module->check();
-#endif
-                               }
-
                                SigSpec pattern;
                                SigSpec with;
                                for (auto &conn : cell->connections()) {