sv_reg_t sv_proc_t::get_intreg(reg_t reg)
{
- uint8_t elwidth = _insn->reg_elwidth(reg, true);
+ //uint8_t elwidth = _insn->reg_elwidth(reg, true);
uint64_t data = _insn->p->get_state()->XPR[reg];
- return sv_reg_t(data, xlen, elwidth);
+ return sv_reg_t(data, xlen, _insn->src_bitwidth);
}
#define GET_REG(name) \
sv_reg_t sv_proc_t::rv_add(sv_reg_t const & lhs, sv_reg_t const & rhs)
{
- uint8_t elwidth = lhs.get_width(rhs);
+ uint8_t bitwidth = _insn->src_bitwidth;
return lhs + rhs;
}
#define sext_bwid(x,wid) (((sreg_t)(x) << (64-wid)) >> (64-wid))
#define zext_bwid(x,wid) (((reg_t)(x) << (64-wid)) >> (64-wid))
+extern int get_bitwidth(uint8_t elwidth, int xlen);
+
+
class sv_sreg_t;
class sv_regbase_t {
uint8_t elwidth;
public:
int get_xlen() const { return xlen; }
- uint8_t get_width() const { return elwidth; }
- uint8_t get_width(sv_regbase_t const&r) const
- {
- // bitfield 0b00=default, 0b01=default/2, 0b10=default*2, 0b11=8-bit
- uint8_t tb[16] = { 0x0, // default-default: default
- 0x0, // default-default/2: default
- 0x2, // default-default*2: default*2
- 0x0, // default-8: default
- 0x0, // default/2-default: default
- 0x1, // default/2-default/2: default/2
- 0x2, // default/2-default*2: default*2
- 0x1, // default/2-8: default*2
- 0x2, // default*2-default: default*2
- 0x2, // default*2-default/2: default*2
- 0x2, // default*2-default*2: default*2
- 0x2, // default*2-8: default*2
- 0x0, // 8-default: default
- 0x1, // 8-default/2: default/2
- 0x2, // 8-default*2: default*2
- 0x3 // 8-8: 8
- };
- return tb[elwidth|(r.elwidth<<2)];
- }
+ uint8_t get_elwidth() const { return elwidth; }
int get_bitwidth() const
{
- switch (elwidth) {
- case 0: return xlen;
- case 1: return xlen / 2;
- case 2: return xlen * 2;
- default: return 8;
- }
+ return ::get_bitwidth(elwidth, xlen);
}
int get_bitwidth(sv_regbase_t const&r) const
{
public:
operator int64_t() const& { return reg; }
- operator sv_reg_t() const& { return sv_reg_t((uint64_t)reg, get_width()); }
+ operator sv_reg_t() const& { return sv_reg_t((uint64_t)reg, get_elwidth()); }
};
inline sv_reg_t::operator sv_sreg_t() const &