Merge branch 'master' into eddie/xilinx_srl
authorEddie Hung <eddie@fpgeh.com>
Mon, 26 Aug 2019 20:56:31 +0000 (13:56 -0700)
committerEddie Hung <eddie@fpgeh.com>
Mon, 26 Aug 2019 20:56:31 +0000 (13:56 -0700)
1  2 
CHANGELOG
techlibs/xilinx/synth_xilinx.cc

diff --cc CHANGELOG
index 5848ae7050ef41a690932f9cdc48128fbb52f74f,113aae8206445f7d99570031392ee65aa9744647..df537b30e8ccf6db1742ab764c94ed3327ea6d03
+++ b/CHANGELOG
@@@ -28,19 -31,15 +31,17 @@@ Yosys 0.9 .. Yosys 0.9-de
      - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
      - Removed "ice40_unlut"
      - Improvements in pmgen: slices, choices, define, generate
 +    - Added "xilinx_srl" for Xilinx shift register extraction
 +    - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl")
  
- Yosys 0.8 .. Yosys 0.8-dev
- --------------------------
+ Yosys 0.8 .. Yosys 0.9
+ ----------------------
  
   * Various
-     - Added $changed support to read_verilog
+     - Many bugfixes and small improvements
+     - Added support for SystemVerilog interfaces and modports
      - Added "write_edif -attrprop"
-     - Added "ice40_unlut" pass
      - Added "opt_lut" pass
-     - Added "synth_ice40 -relut"
-     - Added "synth_ice40 -noabc"
      - Added "gate2lut.v" techmap rule
      - Added "rename -src"
      - Added "equiv_opt" pass
index 5e9cd8a0ebd4e5a7859be3470ec25277fcdf5320,87f4af8f7daa008def5363a46aa74c0b101e4dfe..5f6ad752287093fe213bc760a43ba2227370f3c2
@@@ -377,16 -389,10 +383,18 @@@ struct SynthXilinxPass : public ScriptP
                        run("clean");
                }
  
 +              if (check_label("map_ffs")) {
 +                              if (abc9 || help_mode) {
 +                                              run("techmap -map +/xilinx/ff_map.v", "('-abc9' only)");
 +                                              run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
 +                                                                              "-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT", "('-abc9' only)");
 +                              }
 +              }
 +
                if (check_label("map_luts")) {
                        run("opt_expr -mux_undef");
+                       if (flatten_before_abc)
+                               run("flatten");
                        if (help_mode)
                                run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(option for 'nowidelut', option for '-retime')");
                        else if (abc9) {