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diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index de0864e51d25c013778a93a3f363a307d30cb837..c57f8e370961efef8a630fbb6930036b4cd081d8 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -280,7 +280,25 @@ to D-Form.
 
 This is a standard mode normally found in Vector ISAs.  every element in every source Vector and in the destination uses the same bit of one single predicate mask.
 
-In SVSTATE, for Single-predication, implementors MUST increment both srcstep and dststep: unlike Twin-Predication the two must be equal at all times.
+In SVSTATE, for Single-predication, implementors MUST increment both srcstep and dststep, but depending on whether sz and/or dz are set, srcstep and
+dststep can still potentially become different indices.  Only when sz=dz
+is srcstep guaranteed to equal dststep at all times.
+
+Example 1:
+
+* VL=3
+* mask=0b1101
+* sz=0, dz=1
+
+The following schedule for srcstep and dststep will occur:
+
+| srcstep | dststep | comment      |
+| ----    | -----   | --------      |
+| 0       | 0       | both mask[src=0] and mask[dst=0] are 1 |
+| 1       | 2       | sz=1 but dz=0: dst skips mask[1], src soes not |
+| 2       | 3       | mask[src=2] and mask[dst=3] are 1 |
+
+sz and dz however still interact
 
 # Twin Predication