arch-generic: Making base TLB class a MemObject

Allow configuring a TLB hierarchy using ports

Change-Id: I1f791829d4e072a9104e67eacf69a69de9543634
Reviewed-on: https://gem5-review.googlesource.com/c/14117
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/src/arch/generic/BaseTLB.py b/src/arch/generic/BaseTLB.py
index 6a8a9727fcc18163097e2788dc56ded8f478791c..b98b9935675ea2400d1dc022cfba2397758e5b5d 100644 (file)
--- a/src/arch/generic/BaseTLB.py
+++ b/src/arch/generic/BaseTLB.py
@@ -1,4 +1,5 @@
 # Copyright (c) 2008 The Hewlett-Packard Development Company
+# Copyright (c) 2018 Metempsy Technology Consulting
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -25,10 +26,15 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Authors: Gabe Black
+#          Ivan Pizarro
 
-from m5.SimObject import SimObject
+from m5.params import *
+from MemObject import MemObject
 
-class BaseTLB(SimObject):
+class BaseTLB(MemObject):
     type = 'BaseTLB'
     abstract = True
     cxx_header = "arch/generic/tlb.hh"
+    # Ports to connect with other TLB levels
+    slave  = VectorSlavePort("Port closer to the CPU side")
+    master = MasterPort("Port closer to memory side")

diff --git a/src/arch/generic/tlb.hh b/src/arch/generic/tlb.hh
index 89180341cc33face12e6d79ee9deb9419a251eac..91f8f867bed40c8c43128bffa391550d491ecd4a 100644 (file)
--- a/src/arch/generic/tlb.hh
+++ b/src/arch/generic/tlb.hh
@@ -44,17 +44,17 @@
 #define __ARCH_GENERIC_TLB_HH__
 
 #include "base/logging.hh"
+#include "mem/mem_object.hh"
 #include "mem/request.hh"
-#include "sim/sim_object.hh"
 
 class ThreadContext;
 class BaseMasterPort;
 
-class BaseTLB : public SimObject
+class BaseTLB : public MemObject
 {
   protected:
     BaseTLB(const Params *p)
-        : SimObject(p)
+        : MemObject(p)
     {}
 
   public: