Define YOSYS and SYNTHESIS in preproc

diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index b4e77c31bf53af4c3c5c2dc53f252a354fd61303..4e5d165996e8ca23b23085c64f367e688b6fb8f6 100644 (file)
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -221,7 +221,8 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons
        input_buffer_charp = 0;
 
        input_file(f, filename);
-       defines_map["__YOSYS__"] = "1";
+       defines_map["YOSYS"] = "1";
+       defines_map["SYNTHESIS"] = "1";
 
        while (!input_buffer.empty())
        {