clarify CSRs

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 064a901dcf6ca0ef6347134c159d103a56f898c3..0c8c243f0c616eef4d19a7855b8e90020258be1c 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -69,7 +69,7 @@ tables which are used at the register decode phase.
 * A register CSR key-value table (typically 8 32-bit CSRs of 2 16-bits each)
 * A predication CSR key-value table (again, 8 32-bit CSRs of 2 16-bits each)
 * Small U-Mode and S-Mode register and predication CSR key-value tables
-  (2 16-bit entries each).
+  (2 32-bit CSRs of 2x 16-bit entries each).
 * An optional "reshaping" CSR key-value table which remaps from a 1D
   linear shape to 2D or 3D, including full transposition.