arm: Call pseudoInst directly from the mmapped IPR handlers.

The amount of plumbing necessary for the generic IPR mechanism out
weighs its value, considering it's only used for the m5ops.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-187

Change-Id: I0efcf43904d5f779bef5ad127dd8d39fff41ac39
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23185
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/arch/arm/mmapped_ipr.hh b/src/arch/arm/mmapped_ipr.hh
index d515b837174225394368ebea0d8d5a6725434c4e..1cccdbd79ea3a8542f1a6e156faca0aeb7b0e23b 100644 (file)
--- a/src/arch/arm/mmapped_ipr.hh
+++ b/src/arch/arm/mmapped_ipr.hh
@@ -39,14 +39,44 @@
  * ISA-specific helper functions for memory mapped IPR accesses.
  */
 
-#include "arch/generic/mmapped_ipr.hh"
+#include "base/types.hh"
+#include "mem/packet.hh"
+#include "mem/packet_access.hh"
+#include "sim/pseudo_inst.hh"
+#include "sim/system.hh"
 
 class ThreadContext;
 
 namespace ArmISA
 {
-    using GenericISA::handleIprRead;
-    using GenericISA::handleIprWrite;
+
+inline Cycles
+handleIprRead(ThreadContext *tc, Packet *pkt)
+{
+    Addr addr = pkt->getAddr();
+    auto m5opRange = tc->getSystemPtr()->m5opRange();
+    if (m5opRange.contains(addr)) {
+        uint8_t func;
+        PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
+        uint64_t ret = PseudoInst::pseudoInst<PseudoInstABI>(tc, func);
+        pkt->setLE(ret);
+    }
+    return Cycles(1);
+}
+
+inline Cycles
+handleIprWrite(ThreadContext *tc, Packet *pkt)
+{
+    Addr addr = pkt->getAddr();
+    auto m5opRange = tc->getSystemPtr()->m5opRange();
+    if (m5opRange.contains(addr)) {
+        uint8_t func;
+        PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
+        PseudoInst::pseudoInst<PseudoInstABI>(tc, func);
+    }
+    return Cycles(1);
+}
+
 } // namespace ArmISA
 
 #endif

diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 5ecd7a45c80f0958e42e69df3073fc58e57220c4..5358159fbca0b60972312792cb01f703f933c2bb 100644 (file)
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -138,12 +138,8 @@ TLB::finalizePhysical(const RequestPtr &req,
 {
     const Addr paddr = req->getPaddr();
 
-    if (m5opRange.contains(paddr)) {
-        req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR);
-        req->setPaddr(GenericISA::iprAddressPseudoInst(
-                          (paddr >> 8) & 0xFF,
-                          paddr & 0xFF));
-    }
+    if (m5opRange.contains(paddr))
+        req->setFlags(Request::MMAPPED_IPR);
 
     return NoFault;
 }