radv: port merge tess info from anv

anv merges the tess info correctly, but radv wasn't doing this.

This fixes hangs in
dEQP-VK.tessellation.winding.default_domain.hlsl_triangles_ccw

Fixes: 60fc0544e0 (radv/pipeline: handle tessellation shader compilation)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 1ada69d92f8274f7dc555fb1fdb57e893bba8ca6..903a2945e99b4172a5d4ae6b81b38c70c82b174d 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1769,6 +1769,45 @@ radv_fill_shader_keys(struct ac_shader_variant_key *keys,
        keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
 }
 
+static void
+merge_tess_info(struct shader_info *tes_info,
+                const struct shader_info *tcs_info)
+{
+       /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
+        *
+        *    "PointMode. Controls generation of points rather than triangles
+        *     or lines. This functionality defaults to disabled, and is
+        *     enabled if either shader stage includes the execution mode.
+        *
+        * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
+        * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
+        * and OutputVertices, it says:
+        *
+        *    "One mode must be set in at least one of the tessellation
+        *     shader stages."
+        *
+        * So, the fields can be set in either the TCS or TES, but they must
+        * agree if set in both.  Our backend looks at TES, so bitwise-or in
+        * the values from the TCS.
+        */
+       assert(tcs_info->tess.tcs_vertices_out == 0 ||
+              tes_info->tess.tcs_vertices_out == 0 ||
+              tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
+       tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
+
+       assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
+              tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
+              tcs_info->tess.spacing == tes_info->tess.spacing);
+       tes_info->tess.spacing |= tcs_info->tess.spacing;
+
+       assert(tcs_info->tess.primitive_mode == 0 ||
+              tes_info->tess.primitive_mode == 0 ||
+              tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
+       tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
+       tes_info->tess.ccw |= tcs_info->tess.ccw;
+       tes_info->tess.point_mode |= tcs_info->tess.point_mode;
+}
+
 static
 void radv_create_shaders(struct radv_pipeline *pipeline,
                          struct radv_device *device,
@@ -1872,6 +1911,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
 
        if (nir[MESA_SHADER_TESS_CTRL]) {
                nir_lower_tes_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out);
+               merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
        }
 
        radv_link_shaders(pipeline, nir);