from migen.fhdl.structure import *
from migen.fhdl.structure import _Fragment
from migen.fhdl.specials import Special
-from migen.fhdl.tools import flat_iteration, rename_clock_domain
+from migen.fhdl.tools import rename_clock_domain
+from migen.util.misc import flat_iteration
class FinalizeError(Exception):
pass
-import collections
-
from migen.fhdl.structure import *
from migen.fhdl.structure import _Slice, _Assign
from migen.fhdl.visit import NodeVisitor, NodeTransformer
from migen.fhdl.size import value_bits_sign
-
-def flat_iteration(l):
- for element in l:
- if isinstance(element, collections.Iterable):
- for element2 in flat_iteration(element):
- yield element2
- else:
- yield element
+from migen.util.misc import flat_iteration
class _SignalLister(NodeVisitor):
def __init__(self):
+import collections
+
+def flat_iteration(l):
+ for element in l:
+ if isinstance(element, collections.Iterable):
+ for element2 in flat_iteration(element):
+ yield element2
+ else:
+ yield element
+
def xdir(obj, return_values=False):
for attr in dir(obj):
if attr[:2] != "__" and attr[-2:] != "__":