info->has_tc_compat_zrange_bug = info->chip_class >= GFX8 &&
info->chip_class <= GFX9;
+ info->has_msaa_sample_loc_bug = (info->family >= CHIP_POLARIS10 &&
+ info->family <= CHIP_POLARIS12) ||
+ info->family == CHIP_VEGA10 ||
+ info->family == CHIP_RAVEN;
+
/* Get the number of good compute units. */
info->num_good_compute_units = 0;
for (i = 0; i < info->max_se; i++)
/* Hardware bugs. */
bool has_gfx9_scissor_bug;
bool has_tc_compat_zrange_bug;
+ bool has_msaa_sample_loc_bug;
};
bool ac_query_gpu_info(int fd, void *dev_p,
#include "si_debug_options.h"
}
- sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
- sscreen->info.family <= CHIP_POLARIS12) ||
- sscreen->info.family == CHIP_VEGA10 ||
- sscreen->info.family == CHIP_RAVEN;
sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
sscreen->info.family == CHIP_RAVEN;
sscreen->use_ngg = sscreen->info.chip_class >= GFX10;
bool has_out_of_order_rast;
bool assume_no_z_fights;
bool commutative_blend_add;
- bool has_msaa_sample_loc_bug;
bool has_ls_vgpr_init_bug;
bool dpbb_allowed;
bool dfsm_allowed;
si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
/* Update the small primitive filter workaround if necessary. */
- if (sctx->screen->has_msaa_sample_loc_bug &&
+ if (sctx->screen->info.has_msaa_sample_loc_bug &&
sctx->framebuffer.nr_samples > 1)
si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
}
struct radeon_cmdbuf *cs = sctx->gfx_cs;
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
unsigned nr_samples = sctx->framebuffer.nr_samples;
- bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
+ bool has_msaa_sample_loc_bug = sctx->screen->info.has_msaa_sample_loc_bug;
/* Smoothing (only possible with nr_samples == 1) uses the same
* sample locations as the MSAA it simulates.