Added module->ports

diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc
index f18124e286698d4c4709cb2812af84ee5394e672..9f17f3bfb03538fa534bc023a64608bd1d1a1e78 100644 (file)
--- a/frontends/ast/ast.cc
+++ b/frontends/ast/ast.cc
@@ -919,6 +919,7 @@ static AstModule* process_module(AstNode *ast, bool defer)
        current_module->noopt = flag_noopt;
        current_module->icells = flag_icells;
        current_module->autowire = flag_autowire;
+       current_module->fixup_ports();
        return current_module;
 }
 

diff --git a/frontends/ilang/parser.y b/frontends/ilang/parser.y
index f696140ebd05aff0f13988e7a758dc18ca715b0a..e1ef39a550f70129769a4748394886b406a3f410 100644 (file)
--- a/frontends/ilang/parser.y
+++ b/frontends/ilang/parser.y
@@ -101,6 +101,7 @@ module:
        } module_body TOK_END {
                if (attrbuf.size() != 0)
                        rtlil_frontend_ilang_yyerror("dangling attribute");
+               current_module->fixup_ports();
        } EOL;
 
 module_body:

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 6beaa3fed329d08165cf2357a7480e00566e1e4e..5486f6acb0fa5195e63ddc576c856dfafc40f023 100644 (file)
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -67,7 +67,8 @@ struct CellTypes
        void setup_module(RTLIL::Module *module)
        {
                std::set<RTLIL::IdString> inputs, outputs;
-               for (auto wire : module->wires()) {
+               for (RTLIL::IdString wire_name : module->ports) {
+                       RTLIL::Wire *wire = module->wire(wire_name);
                        if (wire->port_input)
                                inputs.insert(wire->name);
                        if (wire->port_output)

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index fdb33ed82b2106912ae2028b69fb8a622910a26a..96ae0f97a2fa7a607d09cae9c8fb5ccf4e90ed13 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -821,6 +821,8 @@ void RTLIL::Module::check()
                for (auto &it2 : it.second->attributes)
                        log_assert(!it2.first.empty());
                if (it.second->port_id) {
+                       log_assert(SIZE(ports) >= it.second->port_id);
+                       log_assert(ports.at(it.second->port_id-1) == it.first);
                        log_assert(it.second->port_input || it.second->port_output);
                        if (SIZE(ports_declared) < it.second->port_id)
                                ports_declared.resize(it.second->port_id);
@@ -831,6 +833,7 @@ void RTLIL::Module::check()
        }
        for (auto port_declared : ports_declared)
                log_assert(port_declared == true);
+       log_assert(SIZE(ports) == SIZE(ports_declared));
 
        for (auto &it : memories) {
                log_assert(it.first == it.second->name);
@@ -915,6 +918,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const
        RewriteSigSpecWorker rewriteSigSpecWorker;
        rewriteSigSpecWorker.mod = new_mod;
        new_mod->rewrite_sigspecs(rewriteSigSpecWorker);
+       new_mod->fixup_ports();
 }
 
 RTLIL::Module *RTLIL::Module::clone() const
@@ -1154,8 +1158,12 @@ void RTLIL::Module::fixup_ports()
                        w.second->port_id = 0;
 
        std::sort(all_ports.begin(), all_ports.end(), fixup_ports_compare);
-       for (size_t i = 0; i < all_ports.size(); i++)
+
+       ports.clear();
+       for (size_t i = 0; i < all_ports.size(); i++) {
+               ports.push_back(all_ports[i]->name);
                all_ports[i]->port_id = i+1;
+       }
 }
 
 RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width)

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 10da7463653252580b75184ffb3286e54f7902b5..0093b8a1b2933d281e7aab62c099765e8adaafb8 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -575,6 +575,8 @@ public:
        void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
        void new_connections(const std::vector<RTLIL::SigSig> &new_conn);
        const std::vector<RTLIL::SigSig> &connections() const;
+
+       std::vector<RTLIL::IdString> ports;
        void fixup_ports();
 
        template<typename T> void rewrite_sigspecs(T functor);

diff --git a/passes/abc/blifparse.cc b/passes/abc/blifparse.cc
index 1891a74507b3de8849a0e4b41aea72e310d627b1..bc8f343a584e62b7cae0df932c7423afd81cd41f 100644 (file)
--- a/passes/abc/blifparse.cc
+++ b/passes/abc/blifparse.cc
@@ -58,7 +58,6 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
        RTLIL::Const *lutptr = NULL;
        RTLIL::State lut_default_state = RTLIL::State::Sx;
 
-       int port_count = 0;
        module->name = "\\netlist";
        design->add(module);
 
@@ -91,6 +90,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
                                continue;
 
                        if (!strcmp(cmd, ".end")) {
+                               module->fixup_ports();
                                free(buffer);
                                return design;
                        }
@@ -99,7 +99,6 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
                                char *p;
                                while ((p = strtok(NULL, " \t\r\n")) != NULL) {
                                        RTLIL::Wire *wire = module->addWire(stringf("\\%s", p));
-                                       wire->port_id = ++port_count;
                                        if (!strcmp(cmd, ".inputs"))
                                                wire->port_input = true;
                                        else

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 50b4989dfb3524ed4adc9e60286f3259b90d37d7..2f28afb25f1e985018d86dd58c4b8b4219a72740 100644 (file)
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -126,6 +126,8 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
                        wire->port_output = decl.output;
                }
 
+               mod->fixup_ports();
+
                for (auto &para : parameters)
                        log("  ignoring parameter %s.\n", RTLIL::id2cstr(para));
 

diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 89f45e0251a466c7b1f6f7856466601fe54e008b..1b03ab5553cbba296658997adce0d152715bf2ee 100644 (file)
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -106,7 +106,7 @@ struct SubmodWorker
                RTLIL::Module *new_mod = new RTLIL::Module;
                new_mod->name = submod.full_name;
                design->add(new_mod);
-               int port_counter = 1, auto_name_counter = 1;
+               int auto_name_counter = 1;
 
                std::set<RTLIL::IdString> all_wire_names;
                for (auto &it : wire_flags) {
@@ -151,9 +151,6 @@ struct SubmodWorker
                        new_wire->start_offset = wire->start_offset;
                        new_wire->attributes = wire->attributes;
 
-                       if (new_wire->port_input || new_wire->port_output)
-                               new_wire->port_id = port_counter++;
-
                        if (new_wire->port_input && new_wire->port_output)
                                log("  signal %s: inout %s\n", wire->name.c_str(), new_wire->name.c_str());
                        else if (new_wire->port_input)
@@ -166,6 +163,8 @@ struct SubmodWorker
                        flags.new_wire = new_wire;
                }
 
+               new_mod->fixup_ports();
+
                for (RTLIL::Cell *cell : submod.cells) {
                        RTLIL::Cell *new_cell = new_mod->addCell(cell->name, cell);
                        for (auto &conn : new_cell->connections_)

diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 985d51e501a71c02b4825407c1cee004fcfb451b..ebf4d77fc3149d3d64d6415a8559321cc7666735 100644 (file)
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -726,14 +726,14 @@ struct ExtractPass : public Pass {
                                newMod->name = stringf("\\needle%05d_%s_%dx", needleCounter++, id2cstr(haystack_map.at(result.graphId)->name), result.totalMatchesAfterLimits);
                                map->add(newMod);
 
-                               int portCounter = 1;
                                for (auto wire : wires) {
                                        RTLIL::Wire *newWire = newMod->addWire(wire->name, wire->width);
-                                       newWire->port_id = portCounter++;
                                        newWire->port_input = true;
                                        newWire->port_output = true;
                                }
 
+                               newMod->fixup_ports();
+
                                for (auto cell : cells) {
                                        RTLIL::Cell *newCell = newMod->addCell(cell->name, cell->type);
                                        newCell->parameters = cell->parameters;