sort out predicate loop-skip on pack/unpack

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 5edfd674ef180f6f4cc8a6bf9d541dab4f3334aa..ff1f830748c103200f5ad7ff9d6b90a6e0fb5322 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -644,11 +644,12 @@ class StepLoop:
                     break
                 else:
                     srcstep += 1  # advance srcstep
-                    break         # XXX remove this
                     if not self.srcstep_skip:
                         break
-                    if ((1 << srcstep) & srcmask) == 1:
+                    if ((1 << srcstep) & srcmask) != 0:
                         break
+                    else:
+                        log("      sskip", bin(srcmask), bin(1 << srcstep))
         else:
             # advance subvl in *inner* loop
             if end_ssub:
@@ -659,11 +660,12 @@ class StepLoop:
                         break
                     else:
                         srcstep += 1
-                    break # XXX remove this
                     if not self.srcstep_skip:
                         break
-                    if ((1 << srcstep) & srcmask) == 1:
+                    if ((1 << srcstep) & srcmask) != 0:
                         break
+                    else:
+                        log("      sskip", bin(srcmask), bin(1 << srcstep))
                 self.svstate.ssubstep = SelectableInt(0, 2)  # reset
             else:
                 # advance ssubstep
@@ -702,11 +704,12 @@ class StepLoop:
                     break
                 else:
                     dststep += 1  # advance dststep
-                    break         # XXX remove this
                     if not self.dststep_skip:
                         break
-                    if ((1 << dststep) & dstmask) == 1:
+                    if ((1 << dststep) & dstmask) != 0:
                         break
+                    else:
+                        log("      dskip", bin(dstmask), bin(1 << dststep))
         else:
             # advance subvl in *inner* loop
             if end_dsub:
@@ -717,11 +720,12 @@ class StepLoop:
                         break
                     else:
                         dststep += 1
-                    break # XXX remove this
                     if not self.dststep_skip:
                         break
-                    if ((1 << dststep) & dstmask) == 1:
+                    if ((1 << dststep) & dstmask) != 0:
                         break
+                    else:
+                        log("      dskip", bin(dstmask), bin(1 << dststep))
                 self.svstate.dsubstep = SelectableInt(0, 2)  # reset
             else:
                 # advance ssubstep

diff --git a/src/openpower/decoder/isa/test_caller_svp64_pack.py b/src/openpower/decoder/isa/test_caller_svp64_pack.py
index 5c9c7557ea1b1a40ec57ad66813922534b60eb8f..2afc6fdc6bab6b358d5d039e3896e207bda85bfb 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_pack.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_pack.py
@@ -164,7 +164,7 @@ class DecoderTestCase(FHDLTestCase):
         #svstate.maxvl = 2 # MAXVL
         print ("SVSTATE", bin(svstate.asint()))
 
-        mask = 0b1110
+        mask = 0b0110
         initial_regs = [0xffffffff]*64
         initial_regs[3] = mask
         for i in range(8):