targets/kc705: rename sdram_module to sdram_modules to reflect that we have 8 modules...

diff --git a/targets/kc705.py b/targets/kc705.py
index 81eec083a52e093ed4bef2fd19e38a8d5ae24e3e..db6d483427580a94bf0a64093208bd4136defa4a 100644 (file)
--- a/targets/kc705.py
+++ b/targets/kc705.py
@@ -84,14 +84,14 @@ class BaseSoC(SDRAMSoC):
                self.submodules.crg = _CRG(platform)
 
                if not self.with_main_ram:
-                       sdram_module = MT8JTF12864(self.clk_freq)
+                       sdram_modules = MT8JTF12864(self.clk_freq)
                        sdram_controller_settings = sdram.ControllerSettings(
                                req_queue_size=8,
                                read_time=32,
                                write_time=16
                        )
                        self.submodules.ddrphy = k7ddrphy.K7DDRPHY(platform.request("ddram"), memtype="DDR3")
-                       self.register_sdram_phy(self.ddrphy, sdram_module.geom_settings, sdram_module.timing_settings,
+                       self.register_sdram_phy(self.ddrphy, sdram_modules.geom_settings, sdram_modules.timing_settings,
                                sdram_controller_settings)
 
                spiflash_pads = platform.request("spiflash")