Remove submodules.

diff --git a/.gitmodules b/.gitmodules
deleted file mode 100644 (file)
index a683f73..0000000
--- a/.gitmodules
+++ /dev/null
@@ -1,30 +0,0 @@
-[submodule "litex/soc/cores/cpu/lm32/verilog/submodule"]
-       path = litex/soc/cores/cpu/lm32/verilog/submodule
-       url = https://github.com/m-labs/lm32.git
-[submodule "litex/soc/cores/cpu/mor1kx/verilog"]
-       path = litex/soc/cores/cpu/mor1kx/verilog
-       url = https://github.com/openrisc/mor1kx.git
-[submodule "litex/soc/software/compiler_rt"]
-       path = litex/soc/software/compiler_rt
-       url = https://github.com/llvm-mirror/compiler-rt
-[submodule "litex/soc/cores/cpu/picorv32/verilog"]
-       path = litex/soc/cores/cpu/picorv32/verilog
-       url = https://github.com/cliffordwolf/picorv32
-[submodule "litex/build/sim/core/modules/ethernet/tapcfg"]
-       path = litex/build/sim/core/modules/ethernet/tapcfg
-       url = https://github.com/enjoy-digital/tapcfg
-[submodule "litex/soc/cores/cpu/vexriscv/verilog"]
-       path = litex/soc/cores/cpu/vexriscv/verilog
-       url = https://github.com/enjoy-digital/VexRiscv-verilog.git
-[submodule "litex/soc/cores/cpu/minerva/verilog"]
-       path = litex/soc/cores/cpu/minerva/verilog
-       url = https://github.com/lambdaconcept/minerva
-[submodule "litex/soc/cores/cpu/rocket/verilog"]
-       path = litex/soc/cores/cpu/rocket/verilog
-       url = https://github.com/enjoy-digital/rocket-litex-verilog
-[submodule "litex/soc/cores/cpu/microwatt/sources"]
-       path = litex/soc/cores/cpu/microwatt/sources
-       url = https://github.com/antonblanchard/microwatt
-[submodule "litex/soc/cores/cpu/blackparrot/pre-alpha-release"]
-       path = litex/soc/cores/cpu/blackparrot/pre-alpha-release
-       url = https://github.com/enjoy-digital/black-parrot.git

diff --git a/litex/build/sim/core/modules/ethernet/tapcfg b/litex/build/sim/core/modules/ethernet/tapcfg
deleted file mode 160000 (submodule)
index bd557ff..0000000
--- a/litex/build/sim/core/modules/ethernet/tapcfg
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit bd557ff00d8fe2473fcf346e36c96d004e94b8ca

diff --git a/litex/soc/cores/cpu/blackparrot/pre-alpha-release b/litex/soc/cores/cpu/blackparrot/pre-alpha-release
deleted file mode 160000 (submodule)
index dbb13f3..0000000
--- a/litex/soc/cores/cpu/blackparrot/pre-alpha-release
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit dbb13f31370a743633dc94d3639d55c8c4d74e1d

diff --git a/litex/soc/cores/cpu/lm32/verilog/submodule b/litex/soc/cores/cpu/lm32/verilog/submodule
deleted file mode 160000 (submodule)
index 84b3e3c..0000000
--- a/litex/soc/cores/cpu/lm32/verilog/submodule
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 84b3e3ca0ad9535acaef201c1482342871358b08

diff --git a/litex/soc/cores/cpu/microwatt/sources b/litex/soc/cores/cpu/microwatt/sources
deleted file mode 160000 (submodule)
index 1a826f0..0000000
--- a/litex/soc/cores/cpu/microwatt/sources
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 1a826f077bb518bc3ffd799c47a6dd2852165f89

diff --git a/litex/soc/cores/cpu/minerva/verilog b/litex/soc/cores/cpu/minerva/verilog
deleted file mode 160000 (submodule)
index fb296e4..0000000
--- a/litex/soc/cores/cpu/minerva/verilog
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit fb296e4e48e5ced8dd05f2228d84b4bc18f54f75

diff --git a/litex/soc/cores/cpu/mor1kx/verilog b/litex/soc/cores/cpu/mor1kx/verilog
deleted file mode 160000 (submodule)
index 69b97fc..0000000
--- a/litex/soc/cores/cpu/mor1kx/verilog
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 69b97fcb43b35d6c6639ecc68e63d912c09ee8da

diff --git a/litex/soc/cores/cpu/picorv32/verilog b/litex/soc/cores/cpu/picorv32/verilog
deleted file mode 160000 (submodule)
index a9e0ea5..0000000
--- a/litex/soc/cores/cpu/picorv32/verilog
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit a9e0ea54cffa162cfe901ff8d30d8877a18c6d8e

diff --git a/litex/soc/cores/cpu/rocket/verilog b/litex/soc/cores/cpu/rocket/verilog
deleted file mode 160000 (submodule)
index fb31001..0000000
--- a/litex/soc/cores/cpu/rocket/verilog
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit fb31001d9655ebfb8ab25209e094939f68feb6a7

diff --git a/litex/soc/cores/cpu/vexriscv/verilog b/litex/soc/cores/cpu/vexriscv/verilog
deleted file mode 160000 (submodule)
index 8baad21..0000000
--- a/litex/soc/cores/cpu/vexriscv/verilog
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 8baad219885a47f65959a9cd4870691e84678db4

diff --git a/litex/soc/software/compiler_rt b/litex/soc/software/compiler_rt
deleted file mode 160000 (submodule)
index 81fb4f0..0000000
--- a/litex/soc/software/compiler_rt
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 81fb4f00c2cfe13814765968e09931ffa93b5138